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ID | Category [?] | Severity [?] | Reproducibility | Date Submitted | Last Update |
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05409 | Core | Major | Always | Jan 2, 2014, 02:13 | Dec 26, 2016, 00:29 |
Tester | jwdonal | View Status | Public | Platform | MESS (Official Binary) |
Assigned To | Resolution | Open | OS | Windows Vista/7/8 (64-bit) | |
Status [?] | Confirmed | Driver | |||
Version | 0.152 | Fixed in Version | Build | 64-bit | |
Fixed in Git Commit | Github Pull Request # | ||||
Summary | 05409: SNES: SPC-700 does not set processor status flags correctly for TCLR1/TSET1 opcodes | ||||
Description |
From Anomie's spc700.txt we have: TCLR1 !a 4E 3 6 (a) = (a)&~A, ZN as for A-(a) N.....Z. TSET1 !a 0E 3 6 (a) = (a)|A, ZN as for A-(a) N.....Z. It is quite clear from looking at macros OP_TCLR1 and OP_TSET1 in "mess_src_152b\src\emu\cpu\spc700\spc700.c" that the NZ flags are not being set according to A-(a) as Anomie's document states. To fix the problem I just changed the macros as follows: /* Test and Clear Bits */ #define OP_TCLR1(BCLK, MODE) \ CLK(BCLK); \ DST = EA_##MODE(cpustate); \ FLAG_NZ = read_8_##MODE(DST); \ cpustate->spc_int16 = (short)REG_A - (short)(read_8_##MODE(DST)); \ write_8_##MODE(DST, FLAG_NZ & ~REG_A); \ FLAG_NZ = MAKE_UINT_8(cpustate->spc_int16); /* Test and Set Bits */ #define OP_TSET1(BCLK, MODE) \ CLK(BCLK); \ DST = EA_##MODE(cpustate); \ FLAG_NZ = read_8_##MODE(DST); \ cpustate->spc_int16 = (short)REG_A - (short)(read_8_##MODE(DST)); \ write_8_##MODE(DST, FLAG_NZ | REG_A); \ FLAG_NZ = MAKE_UINT_8(cpustate->spc_int16); However, I have not rigorously tested these changes, nor am I very familiar with exactly how the mess source works...so you might want to come up with your own solution. |
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Steps To Reproduce |
A very simple example of the NZ flags not being set correctly would be to run the following instructions on the spc-700. mov $00, #$55 mov A, #$55 tclr1 $0000 From the above, since direct-page location $00 holds the value $55 and since the accumulator A holds the value $55, the Z flag should be set to 1 based on the algorithm A-(a)...but this does not happen. |
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Additional Information | |||||
Github Commit | |||||
Flags | Verified with Code | ||||
Regression Version | |||||
Affected Sets / Systems | SNES | ||||
Attached Files
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