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Viewing Issue Advanced Details
| ID | Category [?] | Severity [?] | Reproducibility | Date Submitted | Last Update |
|---|---|---|---|---|---|
| 05434 | Timing | Minor | Always | Jan 23, 2014, 23:33 | Jan 24, 2014, 18:43 |
| Tester | Alegend45 | View Status | Public | Platform | MESS (Self-compiled) |
| Assigned To | Resolution | Open | OS | Linux | |
| Status [?] | Acknowledged | Driver | |||
| Version | 0.152 | Fixed in Version | Build | 64-bit | |
| Fixed in Git Commit | Github Pull Request # | ||||
| Summary |
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| Description |
This bug occurs in Acid800's CPU timing test, where it states "Incorrect DEX/BNE cycle count: 6." I investigated this, and the culprit, assuming the cycle counts in the 6502 core are correct, is an INC WSYNC instruction, which issues a read, and 2 writes to and from WSYNC, according to how the 6502 does it. This skips 3 scanlines in MESS when Acid800 only expects it to skip one. I have a partial fix for this that makes reads from WSYNC do nothing, as the Altirra Hardware Reference Manual says they do (or at least it says the WSYNC is write-only). Something that should fully fix this would be, according to the same document, making the 6502 core not respond to RDY during write cycles. However, this is beyond my ability. |
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| Steps To Reproduce |
1. Run Acid800 in the a800 driver. 2. Wait for the CPU timing test. |
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| Additional Information | |||||
| Github Commit | |||||
| Flags | Possible | ||||
| Regression Version | |||||
| Affected Sets / Systems | a800 | ||||
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Attached Files
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Partial fix patch [Show Content] [Hide Content]Index: src/mame/video/antic.c
===================================================================
--- src/mame/video/antic.c (revision 27234)
+++ src/mame/video/antic.c (working copy)
@@ -89,9 +89,9 @@
case 9: /* nothing */
data = antic.r.antic09;
break;
- case 10: /* WSYNC read */
- space.machine().device("maincpu")->execute().spin_until_trigger(TRIGGER_HSYNC);
- antic.w.wsync = 1;
+ case 10: /* WSYNC is write only. */
+ //space.machine().device("maincpu")->execute().spin_until_trigger(TRIGGER_HSYNC);
+ //antic.w.wsync = 1;
data = antic.r.antic0a;
break;
case 11: /* vert counter (scanline / 2) */
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