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Viewing Issue Advanced Details
ID | Category [?] | Severity [?] | Reproducibility | Date Submitted | Last Update |
---|---|---|---|---|---|
08751 | Media Support | Major | Always | Sep 1, 2023, 15:02 | Jan 5, 2024, 11:30 |
Tester | Wayder | View Status | Public | Platform | MAME (Official Binary) |
Assigned To | Resolution | Open | OS | Windows 10/11 (64-bit) | |
Status [?] | Acknowledged | Driver | |||
Version | 0.254 | Fixed in Version | Build | 64-bit | |
Fixed in Git Commit | Github Pull Request # | ||||
Summary | 08751: x68000: If a SCSI hard disk is loaded, the floppy disk cannot be accessed. | ||||
Description |
If a SCSI hard disk (.hds) is loaded, the floppy disk cannot be accessed. It worked until Ver. 0.253. |
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Steps To Reproduce | |||||
Additional Information | |||||
Github Commit | |||||
Flags | |||||
Regression Version | |||||
Affected Sets / Systems | x68000 | ||||
Attached Files
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0253_nofd.png (20,027 bytes) Sep 8, 2023, 13:07 Uploaded by Wayder
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0253_infd.png (32,840 bytes) Sep 8, 2023, 13:07 Uploaded by Wayder
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req_sense-error.log.txt (508,738 bytes) Jan 5, 2024, 11:29 Uploaded by grantek Verbose log with mostly vanilla MAME (REQUEST SENSE hooked up) [Show Content] [Hide Content]Soft reset [:exp1:cz6bs1:scsi:7:spc] new state: Idle -> Idle (delay 0, timeout 0) [:crtc] visarea larger then reg[20]: 992x551, 0x0 [:crtc] visarea larger then reg[20]: 992x551, 0x0 [:crtc] visarea larger then reg[20]: 992x551, 0x0 [:crtc] visarea larger then reg[20]: 992x551, 0x0 [:crtc] visarea larger then reg[20]: 992x551, 0x0 [:crtc] visarea larger then reg[20]: 992x551, 0x0 [:crtc] visarea larger then reg[20]: 992x551, 0x0 [:crtc] visarea larger then reg[20]: 992x551, 0x0 [:crtc] visarea larger then reg[20]: 992x551, 0x0 [:crtc] CRTC: Register 20 = 0316 [:crtc] visarea larger then reg[20]: 992x551, 768x512 [:crtc] CRTC: Register 20 = 0b16 [:crtc] visarea larger then reg[20]: 992x551, 768x512 [:keyboard:x68k] KB: LED status set to 7f [:keyboard:x68k] KB: LED status set to 7f [:keyboard:x68k] KB: Keyboard enable bit = 1 [:keyboard:x68k] KB: Keypress delay time is now 500ms [:keyboard:x68k] KB: Keypress repeat rate is now 30ms [:maincpu] ':maincpu' (FF8190): unmapped program memory write to E8C002 = 0101 & 00FF [:x68k_hdc] SASI: SPECIFY [:x68k_hdc] SPECIFY: wrote 0x101 [:x68k_hdc] SPECIFY: wrote 0x101 [:x68k_hdc] SPECIFY: wrote 0x00 [:x68k_hdc] SPECIFY: wrote 0x303 [:x68k_hdc] SPECIFY: wrote 0x202 [:x68k_hdc] SPECIFY: wrote 0x9898 [:x68k_hdc] SPECIFY: wrote 0x8080 [:x68k_hdc] SPECIFY: wrote 0x00 [:x68k_hdc] SPECIFY: wrote 0x00 [:x68k_hdc] SPECIFY: wrote 0x00 [:x68k_hdc] SASI: Write transfer complete [:x68k_hdc] SASI: No HD connected [:x68k_hdc] SASI: REQUEST SENSE [:x68k_hdc] REQUEST SENSE: read value 0x01 [:x68k_hdc] REQUEST SENSE: read value 0x00 [:x68k_hdc] REQUEST SENSE: read value 0x00 [:x68k_hdc] REQUEST SENSE: read value 0x00 [:x68k_hdc] SASI: Read transfer complete [:crtc] visarea larger then reg[20]: 992x551, 768x512 [:crtc] visarea larger then reg[20]: 992x551, 768x512 [:crtc] visarea larger then reg[20]: 992x551, 768x512 [:crtc] visarea larger then reg[20]: 992x551, 768x512 [:crtc] visarea larger then reg[20]: 992x551, 768x512 [:crtc] visarea larger then reg[20]: 992x551, 768x512 [:crtc] visarea larger then reg[20]: 992x551, 768x512 [:crtc] visarea larger then reg[20]: 992x551, 768x512 [:crtc] visarea larger then reg[20]: 992x551, 768x512 [:crtc] CRTC: Register 20 = 0316 [:crtc] visarea larger then reg[20]: 992x551, 768x512 [:crtc] CRTC: Register 20 = 0b16 [:crtc] visarea larger then reg[20]: 992x551, 768x512 [:maincpu] ':maincpu' (FF8190): unmapped program memory write to E8C002 = 0101 & 00FF [:maincpu] ':maincpu' (FF8190): unmapped program memory write to E8C002 = 0101 & 00FF [:x68k_hdc] SASI: SPECIFY [:x68k_hdc] SPECIFY: wrote 0x101 [:x68k_hdc] SPECIFY: wrote 0x101 [:x68k_hdc] SPECIFY: wrote 0x00 [:x68k_hdc] SPECIFY: wrote 0x303 [:x68k_hdc] SPECIFY: wrote 0x202 [:x68k_hdc] SPECIFY: wrote 0x9898 [:x68k_hdc] SPECIFY: wrote 0x8080 [:x68k_hdc] SPECIFY: wrote 0x00 [:x68k_hdc] SPECIFY: wrote 0x00 [:x68k_hdc] SPECIFY: wrote 0x00 [:x68k_hdc] SASI: Write transfer complete [:x68k_hdc] SASI: No HD connected [:x68k_hdc] SASI: REQUEST SENSE [:x68k_hdc] REQUEST SENSE: read value 0x01 [:x68k_hdc] REQUEST SENSE: read value 0x00 [:x68k_hdc] REQUEST SENSE: read value 0x00 [:x68k_hdc] REQUEST SENSE: read value 0x00 [:x68k_hdc] SASI: Read transfer complete [:x68k_hdc] SASI: REZERO UNIT [:x68k_hdc] SASI: SPECIFY [:x68k_hdc] SPECIFY: wrote 0x101 [:x68k_hdc] SPECIFY: wrote 0x101 [:x68k_hdc] SPECIFY: wrote 0x00 [:x68k_hdc] SPECIFY: wrote 0x303 [:x68k_hdc] SPECIFY: wrote 0x202 [:x68k_hdc] SPECIFY: wrote 0x9898 [:x68k_hdc] SPECIFY: wrote 0x8080 [:x68k_hdc] SPECIFY: wrote 0x00 [:x68k_hdc] SPECIFY: wrote 0x00 [:x68k_hdc] SPECIFY: wrote 0x00 [:x68k_hdc] SASI: Write transfer complete [:x68k_hdc] SASI: No HD connected [:x68k_hdc] SASI: REQUEST SENSE [:x68k_hdc] REQUEST SENSE: read value 0x01 [:x68k_hdc] REQUEST SENSE: read value 0x00 [:x68k_hdc] REQUEST SENSE: read value 0x00 [:x68k_hdc] REQUEST SENSE: read value 0x00 [:x68k_hdc] SASI: Read transfer complete [:x68k_hdc] SASI: No HD connected [:x68k_hdc] SASI: REQUEST SENSE [:x68k_hdc] REQUEST SENSE: read value 0x01 [:x68k_hdc] REQUEST SENSE: read value 0x00 [:x68k_hdc] REQUEST SENSE: read value 0x00 [:x68k_hdc] REQUEST SENSE: read value 0x00 [:x68k_hdc] SASI: Read transfer complete [:x68k_hdc] SASI: SPECIFY [:x68k_hdc] SPECIFY: wrote 0x101 [:x68k_hdc] SPECIFY: wrote 0x101 [:x68k_hdc] SPECIFY: wrote 0x00 [:x68k_hdc] SPECIFY: wrote 0x303 [:x68k_hdc] SPECIFY: wrote 0x202 [:x68k_hdc] SPECIFY: wrote 0x9898 [:x68k_hdc] SPECIFY: wrote 0x8080 [:x68k_hdc] SPECIFY: wrote 0x00 [:x68k_hdc] SPECIFY: wrote 0x00 [:x68k_hdc] SPECIFY: wrote 0x00 [:x68k_hdc] SASI: Write transfer complete [:x68k_hdc] SASI: No HD connected [:x68k_hdc] SASI: REQUEST SENSE [:x68k_hdc] REQUEST SENSE: read value 0x01 [:x68k_hdc] REQUEST SENSE: read value 0x00 [:x68k_hdc] REQUEST SENSE: read value 0x00 [:x68k_hdc] REQUEST SENSE: read value 0x00 [:x68k_hdc] SASI: Read transfer complete [:x68k_hdc] SASI: REZERO UNIT [:exp1:cz6bs1:scsi:7:spc] sctl_w: 90 [:exp1:cz6bs1:scsi:7:spc] bdid_w: 07 [:exp1:cz6bs1:scsi:7:spc] scmd_w: 00 [:exp1:cz6bs1:scsi:7:spc] scmd_w: Bus release [:exp1:cz6bs1:scsi:7:spc] pctl_w: 00 [:exp1:cz6bs1:scsi:7:spc] tch_w: 00 [:exp1:cz6bs1:scsi:7:spc] tcm_w: 00 [:exp1:cz6bs1:scsi:7:spc] tcl_w: 00 [:exp1:cz6bs1:scsi:7:spc] temp_w: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 00 TC 0 [:exp1:cz6bs1:scsi:7:spc] sctl_w: 10 [:exp1:cz6bs1:scsi:7:spc] sdgc_w: 00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 00 TC 0 [:exp1:cz6bs1:scsi:7:spc] scmd_w: 10 [:exp1:cz6bs1:scsi:7:spc] scmd_w: Bus release [:exp1:cz6bs1:scsi:7:spc] scmd_w: 00 [:exp1:cz6bs1:scsi:7:spc] scmd_w: Bus release [:exp1:cz6bs1:scsi:7:spc] pctl_w: 00 [:exp1:cz6bs1:scsi:7:spc] bdid_r: 80 [:exp1:cz6bs1:scsi:7:spc] sctl_w: 10 [:exp1:cz6bs1:scsi:7:spc] temp_w: 80 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 00 TC 0 [:exp1:cz6bs1:scsi:7:spc] tcm_w: C4 [:exp1:cz6bs1:scsi:7:spc] tch_w: 09 [:exp1:cz6bs1:scsi:7:spc] tcl_w: 03 [:exp1:cz6bs1:scsi:7:spc] ints_w: 00 [:exp1:cz6bs1:scsi:7:spc] scmd_w: 20 [:exp1:cz6bs1:scsi:7:spc] scmd_w: Select [:exp1:cz6bs1:scsi:7:spc] new state: Idle -> ArbitrationWaitBusFree (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 ArbitrationWaitBusFree, data 00 ctrl 00 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: ArbitrationWaitBusFree -> ArbitrationAssertBSY (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 ArbitrationAssertBSY, data 00 ctrl 00 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: ArbitrationAssertBSY -> ArbitrationWait (delay 32, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 ArbitrationWait, data 80 ctrl 08 TC 640003 [:exp1:cz6bs1:scsi:7:spc] Arbitration won [:exp1:cz6bs1:scsi:7:spc] new state: ArbitrationWait -> ArbitrationAssertSEL (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 ArbitrationAssertSEL, data 80 ctrl 08 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: ArbitrationAssertSEL -> SelectionAssertID (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 SelectionAssertID, data 80 ctrl 18 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: SelectionAssertID -> SelectionAssertSEL (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 SelectionAssertSEL, data 80 ctrl 18 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: SelectionAssertSEL -> SelectionWaitBSY (delay 0, timeout 1280030) [:exp1:cz6bs1:scsi:7:spc] step: 1 SelectionWaitBSY, timeout data 80 ctrl 10 TC 640003 [:exp1:cz6bs1:scsi:7:spc] select timeout [:exp1:cz6bs1:scsi:7:spc] temp_w: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 SelectionWaitBSY, data 80 ctrl 10 TC 0 [:exp1:cz6bs1:scsi:7:spc] select timeout [:exp1:cz6bs1:scsi:7:spc] tcl_w: 58 [:exp1:cz6bs1:scsi:7:spc] tcm_w: 02 [:exp1:cz6bs1:scsi:7:spc] tch_w: 00 [:exp1:cz6bs1:scsi:7:spc] ints_w: 04 [:exp1:cz6bs1:scsi:7:spc] new state: SelectionWaitBSY -> SelectionAssertID (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 SelectionAssertID, data 80 ctrl 10 TC 600 [:exp1:cz6bs1:scsi:7:spc] new state: SelectionAssertID -> SelectionAssertSEL (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 SelectionAssertSEL, data 00 ctrl 10 TC 600 [:exp1:cz6bs1:scsi:7:spc] new state: SelectionAssertSEL -> SelectionWaitBSY (delay 0, timeout 1054) [:exp1:cz6bs1:scsi:7:spc] step: 1 SelectionWaitBSY, timeout data 00 ctrl 10 TC 600 [:exp1:cz6bs1:scsi:7:spc] select timeout [:exp1:cz6bs1:scsi:7:spc] ints_w: 04 [:exp1:cz6bs1:scsi:7:spc] new state: SelectionWaitBSY -> Idle (delay 0, timeout 0) [:exp1:cz6bs1:scsi:7:spc] ints_w: 00 [:exp1:cz6bs1:scsi:7:spc] psns_r: 00 [:exp1:cz6bs1:scsi:7:spc] pctl_w: 00 [:exp1:cz6bs1:scsi:7:spc] bdid_r: 80 [:exp1:cz6bs1:scsi:7:spc] sctl_w: 10 [:exp1:cz6bs1:scsi:7:spc] temp_w: 80 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 00 TC 0 [:exp1:cz6bs1:scsi:7:spc] tcm_w: C4 [:exp1:cz6bs1:scsi:7:spc] tch_w: 09 [:exp1:cz6bs1:scsi:7:spc] tcl_w: 03 [:exp1:cz6bs1:scsi:7:spc] ints_w: 00 [:exp1:cz6bs1:scsi:7:spc] scmd_w: 20 [:exp1:cz6bs1:scsi:7:spc] scmd_w: Select [:exp1:cz6bs1:scsi:7:spc] new state: Idle -> ArbitrationWaitBusFree (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 ArbitrationWaitBusFree, data 00 ctrl 00 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: ArbitrationWaitBusFree -> ArbitrationAssertBSY (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 ArbitrationAssertBSY, data 00 ctrl 00 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: ArbitrationAssertBSY -> ArbitrationWait (delay 32, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 ArbitrationWait, data 80 ctrl 08 TC 640003 [:exp1:cz6bs1:scsi:7:spc] Arbitration won [:exp1:cz6bs1:scsi:7:spc] new state: ArbitrationWait -> ArbitrationAssertSEL (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 ArbitrationAssertSEL, data 80 ctrl 08 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: ArbitrationAssertSEL -> SelectionAssertID (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 SelectionAssertID, data 80 ctrl 18 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: SelectionAssertID -> SelectionAssertSEL (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 SelectionAssertSEL, data 80 ctrl 18 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: SelectionAssertSEL -> SelectionWaitBSY (delay 0, timeout 1280030) [:exp1:cz6bs1:scsi:7:spc] step: 1 SelectionWaitBSY, timeout data 80 ctrl 10 TC 640003 [:exp1:cz6bs1:scsi:7:spc] select timeout [:exp1:cz6bs1:scsi:7:spc] temp_w: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 SelectionWaitBSY, data 80 ctrl 10 TC 0 [:exp1:cz6bs1:scsi:7:spc] select timeout [:exp1:cz6bs1:scsi:7:spc] tcl_w: 58 [:exp1:cz6bs1:scsi:7:spc] tcm_w: 02 [:exp1:cz6bs1:scsi:7:spc] tch_w: 00 [:exp1:cz6bs1:scsi:7:spc] ints_w: 04 [:exp1:cz6bs1:scsi:7:spc] new state: SelectionWaitBSY -> SelectionAssertID (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 SelectionAssertID, data 80 ctrl 10 TC 600 [:exp1:cz6bs1:scsi:7:spc] new state: SelectionAssertID -> SelectionAssertSEL (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 SelectionAssertSEL, data 00 ctrl 10 TC 600 [:exp1:cz6bs1:scsi:7:spc] new state: SelectionAssertSEL -> SelectionWaitBSY (delay 0, timeout 1054) [:exp1:cz6bs1:scsi:7:spc] step: 1 SelectionWaitBSY, timeout data 00 ctrl 10 TC 600 [:exp1:cz6bs1:scsi:7:spc] select timeout [:exp1:cz6bs1:scsi:7:spc] ints_w: 04 [:exp1:cz6bs1:scsi:7:spc] new state: SelectionWaitBSY -> Idle (delay 0, timeout 0) [:exp1:cz6bs1:scsi:7:spc] ints_w: 00 [:exp1:cz6bs1:scsi:7:spc] psns_r: 00 [:exp1:cz6bs1:scsi:7:spc] pctl_w: 00 [:exp1:cz6bs1:scsi:7:spc] bdid_r: 80 [:exp1:cz6bs1:scsi:7:spc] sctl_w: 10 [:exp1:cz6bs1:scsi:7:spc] temp_w: 81 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 00 TC 0 [:exp1:cz6bs1:scsi:7:spc] tcm_w: C4 [:exp1:cz6bs1:scsi:7:spc] tch_w: 09 [:exp1:cz6bs1:scsi:7:spc] tcl_w: 03 [:exp1:cz6bs1:scsi:7:spc] ints_w: 00 [:exp1:cz6bs1:scsi:7:spc] scmd_w: 20 [:exp1:cz6bs1:scsi:7:spc] scmd_w: Select [:exp1:cz6bs1:scsi:7:spc] new state: Idle -> ArbitrationWaitBusFree (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 ArbitrationWaitBusFree, data 00 ctrl 00 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: ArbitrationWaitBusFree -> ArbitrationAssertBSY (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 ArbitrationAssertBSY, data 00 ctrl 00 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: ArbitrationAssertBSY -> ArbitrationWait (delay 32, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 ArbitrationWait, data 80 ctrl 08 TC 640003 [:exp1:cz6bs1:scsi:7:spc] Arbitration won [:exp1:cz6bs1:scsi:7:spc] new state: ArbitrationWait -> ArbitrationAssertSEL (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 ArbitrationAssertSEL, data 80 ctrl 08 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: ArbitrationAssertSEL -> SelectionAssertID (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 SelectionAssertID, data 80 ctrl 18 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: SelectionAssertID -> SelectionAssertSEL (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 SelectionAssertSEL, data 81 ctrl 18 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: SelectionAssertSEL -> SelectionWaitBSY (delay 0, timeout 1280030) [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 18 [:exp1:cz6bs1:scsi:7:spc] step: 1 SelectionWaitBSY, data 81 ctrl 18 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: SelectionWaitBSY -> Selection (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 Selection, data 81 ctrl 18 TC 640003 [:exp1:cz6bs1:scsi:7:spc] selection success [:exp1:cz6bs1:scsi:7:spc] scsi_command_complete [:exp1:cz6bs1:scsi:7:spc] new state: Selection -> Idle (delay 0, timeout 0) [:exp1:cz6bs1:scsi:7:spc] ints_w: 10 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] pctl_w: 02 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] temp_w: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 81 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_put_data, id:0 pos:0 data:00 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4A [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] pctl_w: 02 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] temp_w: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_put_data, id:0 pos:1 data:00 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4A [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] pctl_w: 02 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] temp_w: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_put_data, id:0 pos:2 data:00 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4A [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] pctl_w: 02 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] temp_w: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_put_data, id:0 pos:3 data:00 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4A [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] pctl_w: 02 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] temp_w: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_put_data, id:0 pos:4 data:00 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4A [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] pctl_w: 02 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] temp_w: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_put_data, id:0 pos:5 data:00 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4A [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:0:harddisk] 00 00 00 00 00 00 [:exp1:cz6bs1:scsi:0:harddisk] command TEST UNIT READY [:exp1:cz6bs1:scsi:7:spc] psns_r: 8B [:exp1:cz6bs1:scsi:7:spc] psns_r: 8B [:exp1:cz6bs1:scsi:7:spc] pctl_w: 03 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8B [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:7:spc] psns_r: 4B [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 4B TC 640003 [:exp1:cz6bs1:scsi:7:spc] temp_r: 00 [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] psns_r: 8F [:exp1:cz6bs1:scsi:7:spc] psns_r: 8F [:exp1:cz6bs1:scsi:7:spc] pctl_w: 07 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8F [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:7:spc] psns_r: 4F [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 4F TC 640003 [:exp1:cz6bs1:scsi:7:spc] temp_r: 00 [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 00 TC 640003 [:exp1:cz6bs1:scsi:7:spc] SCSI disconnect [:exp1:cz6bs1:scsi:7:spc] scsi_disconnect: m_tc 640003 [:exp1:cz6bs1:scsi:7:spc] new state: Idle -> Idle (delay 0, timeout 0) [:exp1:cz6bs1:scsi:7:spc] pctl_w: 00 [:exp1:cz6bs1:scsi:7:spc] bdid_r: 80 [:exp1:cz6bs1:scsi:7:spc] sctl_w: 10 [:exp1:cz6bs1:scsi:7:spc] temp_w: 81 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 00 TC 640003 [:exp1:cz6bs1:scsi:7:spc] tcm_w: C4 [:exp1:cz6bs1:scsi:7:spc] tch_w: 09 [:exp1:cz6bs1:scsi:7:spc] tcl_w: 03 [:exp1:cz6bs1:scsi:7:spc] ints_w: 20 [:exp1:cz6bs1:scsi:7:spc] scmd_w: 20 [:exp1:cz6bs1:scsi:7:spc] scmd_w: Select [:exp1:cz6bs1:scsi:7:spc] new state: Idle -> ArbitrationWaitBusFree (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 ArbitrationWaitBusFree, data 00 ctrl 00 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: ArbitrationWaitBusFree -> ArbitrationAssertBSY (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 ArbitrationAssertBSY, data 00 ctrl 00 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: ArbitrationAssertBSY -> ArbitrationWait (delay 32, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 ArbitrationWait, data 80 ctrl 08 TC 640003 [:exp1:cz6bs1:scsi:7:spc] Arbitration won [:exp1:cz6bs1:scsi:7:spc] new state: ArbitrationWait -> ArbitrationAssertSEL (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 ArbitrationAssertSEL, data 80 ctrl 08 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: ArbitrationAssertSEL -> SelectionAssertID (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 SelectionAssertID, data 80 ctrl 18 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: SelectionAssertID -> SelectionAssertSEL (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 SelectionAssertSEL, data 81 ctrl 18 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: SelectionAssertSEL -> SelectionWaitBSY (delay 0, timeout 1280030) [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 18 [:exp1:cz6bs1:scsi:7:spc] step: 1 SelectionWaitBSY, data 81 ctrl 18 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: SelectionWaitBSY -> Selection (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 Selection, data 81 ctrl 18 TC 640003 [:exp1:cz6bs1:scsi:7:spc] selection success [:exp1:cz6bs1:scsi:7:spc] scsi_command_complete [:exp1:cz6bs1:scsi:7:spc] new state: Selection -> Idle (delay 0, timeout 0) [:exp1:cz6bs1:scsi:7:spc] ints_w: 10 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] pctl_w: 02 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] temp_w: 03 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 81 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_put_data, id:0 pos:0 data:03 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4A [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] pctl_w: 02 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] temp_w: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 03 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_put_data, id:0 pos:1 data:00 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4A [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] pctl_w: 02 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] temp_w: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_put_data, id:0 pos:2 data:00 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4A [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] pctl_w: 02 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] temp_w: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_put_data, id:0 pos:3 data:00 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4A [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] pctl_w: 02 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] temp_w: 03 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_put_data, id:0 pos:4 data:03 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4A [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] pctl_w: 02 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] temp_w: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 03 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_put_data, id:0 pos:5 data:00 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4A [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:0:harddisk] 03 00 00 00 03 00 [:exp1:cz6bs1:scsi:0:harddisk] command REQUEST SENSE lun=0 alloc=03 [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:1 pos:0 data:f0 [:exp1:cz6bs1:scsi:7:spc] psns_r: 89 [:exp1:cz6bs1:scsi:7:spc] psns_r: 89 [:exp1:cz6bs1:scsi:7:spc] pctl_w: 01 [:exp1:cz6bs1:scsi:7:spc] tcl_w: 03 [:exp1:cz6bs1:scsi:7:spc] tcm_w: 00 [:exp1:cz6bs1:scsi:7:spc] tch_w: 00 [:exp1:cz6bs1:scsi:7:spc] ints_w: 00 [:exp1:cz6bs1:scsi:7:spc] scmd_w: 80 [:exp1:cz6bs1:scsi:7:spc] DMA Transfer [:exp1:cz6bs1:scsi:7:spc] new state: Idle -> TransferWaitReq (delay 5, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data F0 ctrl 29 TC 3 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data F0 ctrl 29 TC 3 [:exp1:cz6bs1:scsi:7:spc] pushing read data: F0 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data F0 ctrl 29 TC 3 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 3 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 3 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:1 pos:1 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 2 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 2 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 2 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 2 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 2 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 2 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:1 pos:2 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 1 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: F0 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 1 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 1 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 1 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 1 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 1 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 2b [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 2B TC 0 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 2B TC 0 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 2B TC 0 [:exp1:cz6bs1:scsi:7:spc] TransferWaitReq: tc == 0 [:exp1:cz6bs1:scsi:7:spc] scsi_command_complete [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> Idle (delay 0, timeout 0) [:exp1:cz6bs1:scsi:7:spc] ints_w: 10 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8B [:exp1:cz6bs1:scsi:7:spc] psns_r: 8B [:exp1:cz6bs1:scsi:7:spc] pctl_w: 03 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8B [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 4b [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 4B TC 0 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4B [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 4B TC 0 [:exp1:cz6bs1:scsi:7:spc] temp_r: 00 [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 2f [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2F TC 0 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8F [:exp1:cz6bs1:scsi:7:spc] psns_r: 8F [:exp1:cz6bs1:scsi:7:spc] pctl_w: 07 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8F [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 4f [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 4F TC 0 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4F [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 4F TC 0 [:exp1:cz6bs1:scsi:7:spc] temp_r: 00 [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 00 TC 0 [:exp1:cz6bs1:scsi:7:spc] SCSI disconnect [:exp1:cz6bs1:scsi:7:spc] scsi_disconnect: m_tc 0 [:exp1:cz6bs1:scsi:7:spc] new state: Idle -> Idle (delay 0, timeout 0) [:exp1:cz6bs1:scsi:7:spc] pctl_w: 00 [:exp1:cz6bs1:scsi:7:spc] bdid_r: 80 [:exp1:cz6bs1:scsi:7:spc] sctl_w: 10 [:exp1:cz6bs1:scsi:7:spc] temp_w: 81 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 00 TC 0 [:exp1:cz6bs1:scsi:7:spc] tcm_w: C4 [:exp1:cz6bs1:scsi:7:spc] tch_w: 09 [:exp1:cz6bs1:scsi:7:spc] tcl_w: 03 [:exp1:cz6bs1:scsi:7:spc] ints_w: 20 [:exp1:cz6bs1:scsi:7:spc] scmd_w: 20 [:exp1:cz6bs1:scsi:7:spc] scmd_w: Select [:exp1:cz6bs1:scsi:7:spc] new state: Idle -> ArbitrationWaitBusFree (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 ArbitrationWaitBusFree, data 00 ctrl 00 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: ArbitrationWaitBusFree -> ArbitrationAssertBSY (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 ArbitrationAssertBSY, data 00 ctrl 00 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: ArbitrationAssertBSY -> ArbitrationWait (delay 32, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 ArbitrationWait, data 80 ctrl 08 TC 640003 [:exp1:cz6bs1:scsi:7:spc] Arbitration won [:exp1:cz6bs1:scsi:7:spc] new state: ArbitrationWait -> ArbitrationAssertSEL (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 ArbitrationAssertSEL, data 80 ctrl 08 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: ArbitrationAssertSEL -> SelectionAssertID (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 SelectionAssertID, data 80 ctrl 18 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: SelectionAssertID -> SelectionAssertSEL (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 SelectionAssertSEL, data 81 ctrl 18 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: SelectionAssertSEL -> SelectionWaitBSY (delay 0, timeout 1280030) [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 18 [:exp1:cz6bs1:scsi:7:spc] step: 1 SelectionWaitBSY, data 81 ctrl 18 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: SelectionWaitBSY -> Selection (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 Selection, data 81 ctrl 18 TC 640003 [:exp1:cz6bs1:scsi:7:spc] selection success [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 2a [:exp1:cz6bs1:scsi:7:spc] step: 1 Selection, data 81 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scsi_command_complete [:exp1:cz6bs1:scsi:7:spc] new state: Selection -> Idle (delay 0, timeout 0) [:exp1:cz6bs1:scsi:7:spc] ints_w: 10 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] pctl_w: 02 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] temp_w: 12 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 81 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_put_data, id:0 pos:0 data:12 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 4a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 12 ctrl 4A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4A [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 2a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 12 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] pctl_w: 02 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] temp_w: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 12 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_put_data, id:0 pos:1 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 4a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 4A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4A [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 2a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] pctl_w: 02 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] temp_w: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_put_data, id:0 pos:2 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 4a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 4A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4A [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 2a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] pctl_w: 02 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] temp_w: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_put_data, id:0 pos:3 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 4a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 4A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4A [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 2a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] pctl_w: 02 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] temp_w: 24 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_put_data, id:0 pos:4 data:24 $ [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 4a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 24 ctrl 4A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4A [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 2a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 24 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] pctl_w: 02 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] temp_w: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 24 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_put_data, id:0 pos:5 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 4a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 4A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4A [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:0:harddisk] 12 00 00 00 24 00 [:exp1:cz6bs1:scsi:0:harddisk] command INQUIRY lun=0 EVPD=0 page=0 alloc=24 link=00 [:exp1:cz6bs1:scsi:0:harddisk] IDNT tag not found in chd metadata, using default inquiry data [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:0 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 29 TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 89 [:exp1:cz6bs1:scsi:7:spc] psns_r: 89 [:exp1:cz6bs1:scsi:7:spc] pctl_w: 01 [:exp1:cz6bs1:scsi:7:spc] tcl_w: 24 [:exp1:cz6bs1:scsi:7:spc] tcm_w: 00 [:exp1:cz6bs1:scsi:7:spc] tch_w: 00 [:exp1:cz6bs1:scsi:7:spc] ints_w: 00 [:exp1:cz6bs1:scsi:7:spc] scmd_w: 80 [:exp1:cz6bs1:scsi:7:spc] DMA Transfer [:exp1:cz6bs1:scsi:7:spc] new state: Idle -> TransferWaitReq (delay 5, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 36 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 36 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 36 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 36 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 36 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 36 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:1 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 35 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 35 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 35 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 35 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 35 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 35 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:2 data:05 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 05 ctrl 29 TC 34 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 05 ctrl 29 TC 34 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 05 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 05 ctrl 29 TC 34 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 34 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 34 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 34 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:3 data:01 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 01 ctrl 29 TC 33 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 01 ctrl 29 TC 33 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 01 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 01 ctrl 29 TC 33 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 33 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 33 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 33 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:4 data:34 4 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 34 ctrl 29 TC 32 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 34 ctrl 29 TC 32 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 34 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 34 ctrl 29 TC 32 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 32 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 32 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 32 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:5 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 31 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 31 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 31 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 31 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 05 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 31 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 31 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:6 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 30 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 30 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 30 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 30 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 30 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 30 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:7 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 29 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 29 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 01 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 29 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 29 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 29 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:8 data:20 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 20 ctrl 29 TC 28 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 20 ctrl 29 TC 28 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 20 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 20 ctrl 29 TC 28 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 28 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 28 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 28 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:9 data:53 S [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 34 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 53 ctrl 29 TC 27 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 53 ctrl 29 TC 27 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 53 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 53 ctrl 29 TC 27 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 27 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 27 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 27 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:10 data:45 E [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 45 ctrl 29 TC 26 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 45 ctrl 29 TC 26 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 45 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 45 ctrl 29 TC 26 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 26 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 26 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 26 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:11 data:41 A [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 41 ctrl 29 TC 25 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 41 ctrl 29 TC 25 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 41 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 41 ctrl 29 TC 25 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 25 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 25 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 25 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:12 data:47 G [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 47 ctrl 29 TC 24 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 47 ctrl 29 TC 24 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 47 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 47 ctrl 29 TC 24 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 24 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 24 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 24 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:13 data:41 A [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 41 ctrl 29 TC 23 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 41 ctrl 29 TC 23 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 41 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 41 ctrl 29 TC 23 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 23 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 23 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 23 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:14 data:54 T [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 54 ctrl 29 TC 22 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 54 ctrl 29 TC 22 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 54 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 54 ctrl 29 TC 22 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 22 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 22 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:15 data:45 E [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 45 ctrl 29 TC 21 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 45 ctrl 29 TC 21 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 45 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 45 ctrl 29 TC 21 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 21 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 21 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 21 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:16 data:20 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 20 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 20 ctrl 29 TC 20 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 20 ctrl 29 TC 20 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 20 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 20 ctrl 29 TC 20 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 20 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 20 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 20 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:17 data:20 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 20 ctrl 29 TC 19 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 20 ctrl 29 TC 19 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 53 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 20 ctrl 29 TC 19 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 20 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 20 ctrl 29 TC 19 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 19 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 19 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 19 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:18 data:20 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 20 ctrl 29 TC 18 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 20 ctrl 29 TC 18 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 45 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 20 ctrl 29 TC 18 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 20 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 20 ctrl 29 TC 18 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 18 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 18 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 18 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:19 data:20 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 20 ctrl 29 TC 17 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 20 ctrl 29 TC 17 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 41 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 20 ctrl 29 TC 17 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 20 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 20 ctrl 29 TC 17 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 17 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 17 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 17 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:20 data:20 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 20 ctrl 29 TC 16 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 20 ctrl 29 TC 16 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 47 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 20 ctrl 29 TC 16 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 20 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 20 ctrl 29 TC 16 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 16 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 16 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 16 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:21 data:20 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 20 ctrl 29 TC 15 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 20 ctrl 29 TC 15 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 41 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 20 ctrl 29 TC 15 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 20 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 20 ctrl 29 TC 15 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 15 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 15 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 15 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:22 data:20 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 20 ctrl 29 TC 14 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 20 ctrl 29 TC 14 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 54 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 20 ctrl 29 TC 14 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 20 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 20 ctrl 29 TC 14 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 14 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 14 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 14 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:23 data:20 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 20 ctrl 29 TC 13 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 20 ctrl 29 TC 13 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 45 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 20 ctrl 29 TC 13 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 20 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 20 ctrl 29 TC 13 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 13 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 13 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 13 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:24 data:20 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 20 ctrl 29 TC 12 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 20 ctrl 29 TC 12 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 20 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 20 ctrl 29 TC 12 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 20 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 20 ctrl 29 TC 12 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 12 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 12 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 12 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:25 data:20 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 20 ctrl 29 TC 11 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 20 ctrl 29 TC 11 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 20 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 20 ctrl 29 TC 11 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 20 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 20 ctrl 29 TC 11 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 11 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 11 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 11 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:26 data:53 S [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 53 ctrl 29 TC 10 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 53 ctrl 29 TC 10 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 20 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 53 ctrl 29 TC 10 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 53 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 53 ctrl 29 TC 10 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 10 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 10 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 10 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:27 data:54 T [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 54 ctrl 29 TC 9 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 54 ctrl 29 TC 9 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 20 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 54 ctrl 29 TC 9 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 54 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 54 ctrl 29 TC 9 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 9 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 9 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 9 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:28 data:32 2 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 32 ctrl 29 TC 8 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 32 ctrl 29 TC 8 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 20 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 32 ctrl 29 TC 8 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 32 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 32 ctrl 29 TC 8 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 8 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 8 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 8 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:29 data:32 2 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 32 ctrl 29 TC 7 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 32 ctrl 29 TC 7 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 20 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 32 ctrl 29 TC 7 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 32 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 32 ctrl 29 TC 7 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 7 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 7 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 7 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:30 data:35 5 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 35 ctrl 29 TC 6 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 35 ctrl 29 TC 6 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 20 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 35 ctrl 29 TC 6 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 35 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 35 ctrl 29 TC 6 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 6 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 6 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 6 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:31 data:4e N [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 4E ctrl 29 TC 5 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 4E ctrl 29 TC 5 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 20 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 4E ctrl 29 TC 5 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 4E [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 4E ctrl 29 TC 5 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 5 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 5 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 5 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:32 data:31 1 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 31 ctrl 29 TC 4 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 31 ctrl 29 TC 4 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 20 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 31 ctrl 29 TC 4 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 31 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 31 ctrl 29 TC 4 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 4 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 4 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 4 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:33 data:2e . [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 2E ctrl 29 TC 3 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 2E ctrl 29 TC 3 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 20 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 2E ctrl 29 TC 3 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 2E [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 2E ctrl 29 TC 3 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 3 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 3 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 3 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:34 data:30 0 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 30 ctrl 29 TC 2 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 30 ctrl 29 TC 2 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 53 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 30 ctrl 29 TC 2 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 30 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 30 ctrl 29 TC 2 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 2 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 2 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 2 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:35 data:30 0 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 30 ctrl 29 TC 1 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 30 ctrl 29 TC 1 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 54 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 30 ctrl 29 TC 1 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 30 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 30 ctrl 29 TC 1 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 1 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 1 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 1 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 2b [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 2B TC 0 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 32 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 2B TC 0 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 32 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 2B TC 0 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 35 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 2B TC 0 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 4E [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 2B TC 0 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 31 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 2B TC 0 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 2E [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 2B TC 0 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 30 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 2B TC 0 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 30 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 2B TC 0 [:exp1:cz6bs1:scsi:7:spc] TransferWaitReq: tc == 0 [:exp1:cz6bs1:scsi:7:spc] scsi_command_complete [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> Idle (delay 0, timeout 0) [:exp1:cz6bs1:scsi:7:spc] ints_w: 10 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8B [:exp1:cz6bs1:scsi:7:spc] psns_r: 8B [:exp1:cz6bs1:scsi:7:spc] pctl_w: 03 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8B [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 4b [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 4B TC 0 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4B [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 4B TC 0 [:exp1:cz6bs1:scsi:7:spc] temp_r: 00 [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 2f [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2F TC 0 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8F [:exp1:cz6bs1:scsi:7:spc] psns_r: 8F [:exp1:cz6bs1:scsi:7:spc] pctl_w: 07 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8F [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 4f [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 4F TC 0 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4F [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 4F TC 0 [:exp1:cz6bs1:scsi:7:spc] temp_r: 00 [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 00 TC 0 [:exp1:cz6bs1:scsi:7:spc] SCSI disconnect [:exp1:cz6bs1:scsi:7:spc] scsi_disconnect: m_tc 0 [:exp1:cz6bs1:scsi:7:spc] new state: Idle -> Idle (delay 0, timeout 0) [:exp1:cz6bs1:scsi:7:spc] pctl_w: 00 [:exp1:cz6bs1:scsi:7:spc] bdid_r: 80 [:exp1:cz6bs1:scsi:7:spc] sctl_w: 10 [:exp1:cz6bs1:scsi:7:spc] temp_w: 81 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 00 TC 0 [:exp1:cz6bs1:scsi:7:spc] tcm_w: C4 [:exp1:cz6bs1:scsi:7:spc] tch_w: 09 [:exp1:cz6bs1:scsi:7:spc] tcl_w: 03 [:exp1:cz6bs1:scsi:7:spc] ints_w: 20 [:exp1:cz6bs1:scsi:7:spc] scmd_w: 20 [:exp1:cz6bs1:scsi:7:spc] scmd_w: Select [:exp1:cz6bs1:scsi:7:spc] new state: Idle -> ArbitrationWaitBusFree (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 ArbitrationWaitBusFree, data 00 ctrl 00 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: ArbitrationWaitBusFree -> ArbitrationAssertBSY (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 ArbitrationAssertBSY, data 00 ctrl 00 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: ArbitrationAssertBSY -> ArbitrationWait (delay 32, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 ArbitrationWait, data 80 ctrl 08 TC 640003 [:exp1:cz6bs1:scsi:7:spc] Arbitration won [:exp1:cz6bs1:scsi:7:spc] new state: ArbitrationWait -> ArbitrationAssertSEL (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 ArbitrationAssertSEL, data 80 ctrl 08 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: ArbitrationAssertSEL -> SelectionAssertID (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 SelectionAssertID, data 80 ctrl 18 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: SelectionAssertID -> SelectionAssertSEL (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 SelectionAssertSEL, data 81 ctrl 18 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: SelectionAssertSEL -> SelectionWaitBSY (delay 0, timeout 1280030) [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 18 [:exp1:cz6bs1:scsi:7:spc] step: 1 SelectionWaitBSY, data 81 ctrl 18 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: SelectionWaitBSY -> Selection (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 Selection, data 81 ctrl 18 TC 640003 [:exp1:cz6bs1:scsi:7:spc] selection success [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 2a [:exp1:cz6bs1:scsi:7:spc] step: 1 Selection, data 81 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scsi_command_complete [:exp1:cz6bs1:scsi:7:spc] new state: Selection -> Idle (delay 0, timeout 0) [:exp1:cz6bs1:scsi:7:spc] ints_w: 10 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] pctl_w: 02 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] temp_w: 25 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 81 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_put_data, id:0 pos:0 data:25 % [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 4a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 25 ctrl 4A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4A [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 2a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 25 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] pctl_w: 02 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] temp_w: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 25 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_put_data, id:0 pos:1 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 4a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 4A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4A [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 2a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] pctl_w: 02 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] temp_w: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_put_data, id:0 pos:2 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 4a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 4A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4A [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 2a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] pctl_w: 02 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] temp_w: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_put_data, id:0 pos:3 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 4a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 4A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4A [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 2a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] pctl_w: 02 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] temp_w: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_put_data, id:0 pos:4 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 4a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 4A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4A [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 2a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] pctl_w: 02 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] temp_w: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_put_data, id:0 pos:5 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 4a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 4A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4A [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 2a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] pctl_w: 02 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] temp_w: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_put_data, id:0 pos:6 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 4a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 4A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4A [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 2a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] pctl_w: 02 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] temp_w: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_put_data, id:0 pos:7 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 4a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 4A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4A [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 2a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] pctl_w: 02 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] temp_w: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_put_data, id:0 pos:8 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 4a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 4A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4A [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 2a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] pctl_w: 02 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] temp_w: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_put_data, id:0 pos:9 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 4a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 4A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4A [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:0:harddisk] 25 00 00 00 00 00 [:exp1:cz6bs1:scsi:0:harddisk] command READ CAPACITY [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:0 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 29 TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 89 [:exp1:cz6bs1:scsi:7:spc] psns_r: 89 [:exp1:cz6bs1:scsi:7:spc] pctl_w: 01 [:exp1:cz6bs1:scsi:7:spc] tcl_w: 08 [:exp1:cz6bs1:scsi:7:spc] tcm_w: 00 [:exp1:cz6bs1:scsi:7:spc] tch_w: 00 [:exp1:cz6bs1:scsi:7:spc] ints_w: 00 [:exp1:cz6bs1:scsi:7:spc] scmd_w: 80 [:exp1:cz6bs1:scsi:7:spc] DMA Transfer [:exp1:cz6bs1:scsi:7:spc] new state: Idle -> TransferWaitReq (delay 5, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 8 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 8 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 8 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 8 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 8 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 8 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:1 data:18 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 18 ctrl 29 TC 7 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 18 ctrl 29 TC 7 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 18 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 18 ctrl 29 TC 7 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 7 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 7 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 7 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:2 data:49 I [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 49 ctrl 29 TC 6 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 49 ctrl 29 TC 6 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 49 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 49 ctrl 29 TC 6 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 6 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 6 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 6 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:3 data:4f O [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 4F ctrl 29 TC 5 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 4F ctrl 29 TC 5 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 4F [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 4F ctrl 29 TC 5 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 5 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 5 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 18 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 5 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:4 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 4 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 4 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 4 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 4 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 4 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 4 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:5 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 3 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 3 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 3 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 3 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 3 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 3 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:6 data:02 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 02 ctrl 29 TC 2 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 02 ctrl 29 TC 2 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 02 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 02 ctrl 29 TC 2 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 2 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 2 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 2 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:0 pos:7 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 1 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 1 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 4F [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 1 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 1 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 1 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 2b [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 2B TC 0 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 2B TC 0 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 2B TC 0 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 02 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 2B TC 0 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 2B TC 0 [:exp1:cz6bs1:scsi:7:spc] TransferWaitReq: tc == 0 [:exp1:cz6bs1:scsi:7:spc] scsi_command_complete [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> Idle (delay 0, timeout 0) [:exp1:cz6bs1:scsi:7:spc] ints_w: 10 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8B [:exp1:cz6bs1:scsi:7:spc] psns_r: 8B [:exp1:cz6bs1:scsi:7:spc] pctl_w: 03 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8B [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 4b [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 4B TC 0 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4B [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 4B TC 0 [:exp1:cz6bs1:scsi:7:spc] temp_r: 00 [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 2f [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2F TC 0 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8F [:exp1:cz6bs1:scsi:7:spc] psns_r: 8F [:exp1:cz6bs1:scsi:7:spc] pctl_w: 07 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8F [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 4f [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 4F TC 0 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4F [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 4F TC 0 [:exp1:cz6bs1:scsi:7:spc] temp_r: 00 [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 00 TC 0 [:exp1:cz6bs1:scsi:7:spc] SCSI disconnect [:exp1:cz6bs1:scsi:7:spc] scsi_disconnect: m_tc 0 [:exp1:cz6bs1:scsi:7:spc] new state: Idle -> Idle (delay 0, timeout 0) [:exp1:cz6bs1:scsi:7:spc] pctl_w: 00 [:exp1:cz6bs1:scsi:7:spc] bdid_r: 80 [:exp1:cz6bs1:scsi:7:spc] sctl_w: 10 [:exp1:cz6bs1:scsi:7:spc] temp_w: 81 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 00 TC 0 [:exp1:cz6bs1:scsi:7:spc] tcm_w: C4 [:exp1:cz6bs1:scsi:7:spc] tch_w: 09 [:exp1:cz6bs1:scsi:7:spc] tcl_w: 03 [:exp1:cz6bs1:scsi:7:spc] ints_w: 20 [:exp1:cz6bs1:scsi:7:spc] scmd_w: 20 [:exp1:cz6bs1:scsi:7:spc] scmd_w: Select [:exp1:cz6bs1:scsi:7:spc] new state: Idle -> ArbitrationWaitBusFree (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 ArbitrationWaitBusFree, data 00 ctrl 00 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: ArbitrationWaitBusFree -> ArbitrationAssertBSY (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 ArbitrationAssertBSY, data 00 ctrl 00 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: ArbitrationAssertBSY -> ArbitrationWait (delay 32, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 ArbitrationWait, data 80 ctrl 08 TC 640003 [:exp1:cz6bs1:scsi:7:spc] Arbitration won [:exp1:cz6bs1:scsi:7:spc] new state: ArbitrationWait -> ArbitrationAssertSEL (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 ArbitrationAssertSEL, data 80 ctrl 08 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: ArbitrationAssertSEL -> SelectionAssertID (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 SelectionAssertID, data 80 ctrl 18 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: SelectionAssertID -> SelectionAssertSEL (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 SelectionAssertSEL, data 81 ctrl 18 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: SelectionAssertSEL -> SelectionWaitBSY (delay 0, timeout 1280030) [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 18 [:exp1:cz6bs1:scsi:7:spc] step: 1 SelectionWaitBSY, data 81 ctrl 18 TC 640003 [:exp1:cz6bs1:scsi:7:spc] new state: SelectionWaitBSY -> Selection (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 Selection, data 81 ctrl 18 TC 640003 [:exp1:cz6bs1:scsi:7:spc] selection success [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 2a [:exp1:cz6bs1:scsi:7:spc] step: 1 Selection, data 81 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scsi_command_complete [:exp1:cz6bs1:scsi:7:spc] new state: Selection -> Idle (delay 0, timeout 0) [:exp1:cz6bs1:scsi:7:spc] ints_w: 10 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] pctl_w: 02 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] temp_w: 08 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 81 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_put_data, id:0 pos:0 data:08 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 4a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 08 ctrl 4A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4A [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 2a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 08 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] pctl_w: 02 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] temp_w: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 08 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_put_data, id:0 pos:1 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 4a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 4A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4A [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 2a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] pctl_w: 02 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] temp_w: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_put_data, id:0 pos:2 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 4a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 4A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4A [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 2a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] pctl_w: 02 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] temp_w: 04 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_put_data, id:0 pos:3 data:04 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 4a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 04 ctrl 4A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4A [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 2a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 04 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] pctl_w: 02 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] temp_w: 02 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 04 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_put_data, id:0 pos:4 data:02 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 4a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 02 ctrl 4A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4A [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 2a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 02 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] pctl_w: 02 [:exp1:cz6bs1:scsi:7:spc] psns_r: 8A [:exp1:cz6bs1:scsi:7:spc] temp_w: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 02 ctrl 2A TC 640003 [:exp1:cz6bs1:scsi:7:spc] scmd_w: EC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Set ACK/REQ [:exp1:cz6bs1:scsi:7:spc] set ACK [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_put_data, id:0 pos:5 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 4a [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 00 ctrl 4A TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 4A [:exp1:cz6bs1:scsi:7:spc] scmd_w: CC [:exp1:cz6bs1:scsi:7:spc] scmd_w: Reset ACK/REQ [:exp1:cz6bs1:scsi:0:harddisk] command READ start=00000004 blocks=0002 [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:0 data:58 X [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 Idle, data 58 ctrl 29 TC 640003 [:exp1:cz6bs1:scsi:7:spc] psns_r: 89 [:exp1:cz6bs1:scsi:7:spc] psns_r: 89 [:exp1:cz6bs1:scsi:7:spc] pctl_w: 01 [:exp1:cz6bs1:scsi:7:spc] tcl_w: 00 [:exp1:cz6bs1:scsi:7:spc] tcm_w: 04 [:exp1:cz6bs1:scsi:7:spc] tch_w: 00 [:exp1:cz6bs1:scsi:7:spc] ints_w: 00 [:exp1:cz6bs1:scsi:7:spc] scmd_w: 80 [:exp1:cz6bs1:scsi:7:spc] DMA Transfer [:exp1:cz6bs1:scsi:7:spc] new state: Idle -> TransferWaitReq (delay 5, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 58 ctrl 29 TC 1024 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 58 ctrl 29 TC 1024 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 58 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 58 ctrl 29 TC 1024 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 1024 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 1024 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 1024 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:1 data:36 6 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 36 ctrl 29 TC 1023 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 36 ctrl 29 TC 1023 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 36 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 36 ctrl 29 TC 1023 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 1023 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 1023 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 1023 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:2 data:38 8 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 38 ctrl 29 TC 1022 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 38 ctrl 29 TC 1022 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 38 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 38 ctrl 29 TC 1022 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 1022 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 1022 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 1022 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:3 data:4b K [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 4B ctrl 29 TC 1021 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 4B ctrl 29 TC 1021 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 4B [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 4B ctrl 29 TC 1021 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 1021 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 1021 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 1021 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:4 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 1020 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 1020 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 1020 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 1020 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 1020 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 1020 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:5 data:0c [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 0C ctrl 29 TC 1019 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 0C ctrl 29 TC 1019 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 0C [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 0C ctrl 29 TC 1019 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 1019 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 1019 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 1019 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:6 data:24 $ [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 24 ctrl 29 TC 1018 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 24 ctrl 29 TC 1018 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 24 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 24 ctrl 29 TC 1018 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 1018 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 1018 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 1018 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:7 data:a7 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data A7 ctrl 29 TC 1017 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data A7 ctrl 29 TC 1017 [:exp1:cz6bs1:scsi:7:spc] pushing read data: A7 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data A7 ctrl 29 TC 1017 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 1017 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 1017 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 1017 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:8 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 1016 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 1016 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 58 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 1016 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 36 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 1016 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 38 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 1016 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 4B [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 1016 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:9 data:0c [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 0C ctrl 29 TC 1015 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 0C ctrl 29 TC 1015 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 0C [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 0C [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 0C ctrl 29 TC 1015 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 24 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 1015 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: A7 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 1015 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:10 data:24 $ [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 24 ctrl 29 TC 1014 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 24 ctrl 29 TC 1014 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 24 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 0C [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 24 ctrl 29 TC 1014 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 24 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 1014 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 24 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 1014 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:11 data:a7 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 24 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data A7 ctrl 29 TC 1013 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data A7 ctrl 29 TC 1013 [:exp1:cz6bs1:scsi:7:spc] pushing read data: A7 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: A7 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data A7 ctrl 29 TC 1013 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: A7 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 1013 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: A7 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 1013 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:12 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: A7 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 1012 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 1012 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 1012 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 1012 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 1012 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:13 data:0c [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 0C ctrl 29 TC 1011 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 0C ctrl 29 TC 1011 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 0C [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 0C [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 0C ctrl 29 TC 1011 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 0C [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 1011 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 0C [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 1011 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:14 data:24 $ [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 0C [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 24 ctrl 29 TC 1010 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 24 ctrl 29 TC 1010 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 24 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 24 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 24 ctrl 29 TC 1010 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 24 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 1010 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 24 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 1010 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:15 data:a7 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 24 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data A7 ctrl 29 TC 1009 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data A7 ctrl 29 TC 1009 [:exp1:cz6bs1:scsi:7:spc] pushing read data: A7 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: A7 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data A7 ctrl 29 TC 1009 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: A7 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 1009 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: A7 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 1009 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:16 data:48 H [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: A7 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 48 ctrl 29 TC 1008 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 48 ctrl 29 TC 1008 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 48 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 48 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 48 ctrl 29 TC 1008 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 48 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 1008 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 48 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 1008 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:17 data:75 u [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 48 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 75 ctrl 29 TC 1007 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 75 ctrl 29 TC 1007 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 75 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 75 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 75 ctrl 29 TC 1007 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 75 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 1007 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 75 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 1007 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:18 data:6d m [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 75 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 6D ctrl 29 TC 1006 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 6D ctrl 29 TC 1006 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 6D [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 6D [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 6D ctrl 29 TC 1006 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 6D [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 1006 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 6D [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 1006 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:19 data:61 a [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 6D [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 61 ctrl 29 TC 1005 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 61 ctrl 29 TC 1005 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 61 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 61 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 61 ctrl 29 TC 1005 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 61 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 1005 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 61 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 1005 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:20 data:6e n [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 61 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 6E ctrl 29 TC 1004 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 6E ctrl 29 TC 1004 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 6E [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 6E [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 6E ctrl 29 TC 1004 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 6E [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 1004 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 6E [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 1004 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:21 data:36 6 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 6E [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 36 ctrl 29 TC 1003 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 36 ctrl 29 TC 1003 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 36 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 36 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 36 ctrl 29 TC 1003 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 36 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 1003 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 36 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 1003 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:22 data:38 8 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 36 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 38 ctrl 29 TC 1002 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 38 ctrl 29 TC 1002 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 38 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 38 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 38 ctrl 29 TC 1002 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 38 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 1002 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 38 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 1002 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:23 data:6b k [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 38 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 6B ctrl 29 TC 1001 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 6B ctrl 29 TC 1001 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 6B [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 6B [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 6B ctrl 29 TC 1001 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 6B [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 1001 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 6B [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 1001 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:24 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 6B [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 1000 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 1000 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 1000 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 1000 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 1000 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:25 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 999 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 999 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 999 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 999 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 999 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:26 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 998 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 998 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 998 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 998 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 998 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:27 data:20 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 20 ctrl 29 TC 997 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 20 ctrl 29 TC 997 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 20 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 20 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 20 ctrl 29 TC 997 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 20 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 997 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 20 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 997 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:28 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 20 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 996 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 996 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 996 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 996 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 996 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:29 data:0c [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 0C ctrl 29 TC 995 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 0C ctrl 29 TC 995 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 0C [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 0C [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 0C ctrl 29 TC 995 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 0C [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 995 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 0C [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 995 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:30 data:24 $ [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 0C [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 24 ctrl 29 TC 994 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 24 ctrl 29 TC 994 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 24 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 24 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 24 ctrl 29 TC 994 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 24 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 994 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 24 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 994 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:31 data:87 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 24 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 87 ctrl 29 TC 993 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 87 ctrl 29 TC 993 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 87 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 87 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 87 ctrl 29 TC 993 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 87 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 993 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 87 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 993 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:32 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 87 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 992 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 992 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 992 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 992 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 992 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:33 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 991 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 991 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 991 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 991 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 991 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:34 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 990 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 990 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 990 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 990 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 990 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:35 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 989 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 989 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 989 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 989 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 989 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:36 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 988 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 988 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 988 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 988 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 988 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:37 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 987 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 987 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 987 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 987 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 987 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:38 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 986 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 986 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 986 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 986 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 986 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:39 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 985 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 985 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 985 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 985 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 985 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:40 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 984 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 984 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 984 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 984 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 984 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:41 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 983 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 983 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 983 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 983 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 983 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:42 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 982 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 982 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 982 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 982 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 982 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:43 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 981 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 981 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 981 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 981 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 981 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:44 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 980 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 980 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 980 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 980 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 980 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:45 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 979 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 979 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 979 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 979 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 979 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:46 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 978 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 978 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 978 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 978 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 978 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:47 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 977 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 977 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 977 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 977 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 977 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:48 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 976 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 976 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 976 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 976 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 976 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:49 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 975 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 975 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 975 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 975 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 975 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:50 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 974 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 974 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 974 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 974 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 974 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:51 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 973 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 973 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 973 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 973 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 973 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:52 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 972 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 972 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 972 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 972 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 972 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:53 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 971 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 971 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 971 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 971 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 971 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:54 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 970 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 970 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 970 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 970 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 970 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:55 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 969 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 969 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 969 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 969 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 969 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:56 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 968 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 968 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 968 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 968 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 968 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:57 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 967 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 967 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 967 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 967 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 967 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:58 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 966 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 966 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 966 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 966 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 966 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:59 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 965 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 965 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 965 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 965 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 965 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:60 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 964 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 964 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 964 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 964 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 964 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:61 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 963 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 963 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 963 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 963 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 963 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:62 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 962 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 962 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 962 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 962 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 962 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:63 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 961 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 961 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 961 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 961 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 961 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:64 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 960 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 960 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 960 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 960 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 960 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:65 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 959 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 959 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 959 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 959 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 959 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:66 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 958 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 958 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 958 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 958 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 958 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:67 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 957 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 957 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 957 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 957 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 957 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:68 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 956 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 956 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 956 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 956 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 956 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:69 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 955 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 955 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 955 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 955 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 955 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:70 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 954 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 954 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 954 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 954 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 954 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:71 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 953 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 953 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 953 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 953 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 953 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:72 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 952 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 952 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 952 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 952 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 952 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 952 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:73 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 951 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 951 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 951 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 951 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 951 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 951 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:74 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 950 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 950 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 950 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 950 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 950 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 950 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:75 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 949 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 949 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 949 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 949 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 949 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 949 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:76 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 948 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 948 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 948 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 948 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 948 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 948 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:77 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 947 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 947 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 947 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 947 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 947 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 947 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:78 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 946 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 946 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 946 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 946 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 946 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 946 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:79 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 945 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 945 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 945 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 945 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 945 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 945 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:80 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 944 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 944 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 944 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 944 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 944 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 944 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:81 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 943 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 943 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 943 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 943 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 943 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:82 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 942 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 942 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 942 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 942 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 942 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:83 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 941 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 941 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 941 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 941 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 941 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:84 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 940 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 940 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 940 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 940 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 940 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:85 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 939 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 939 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 939 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 939 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 939 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:86 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 938 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 938 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 938 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 938 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 938 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:87 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 937 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 937 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 937 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 937 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 937 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:88 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 936 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 936 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 936 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 936 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 936 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:89 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 935 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 935 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 935 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 935 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 935 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:90 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 934 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 934 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 934 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 934 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 934 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:91 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 933 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 933 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 933 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 933 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 933 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:92 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 932 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 932 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 932 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 932 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 932 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:93 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 931 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 931 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 931 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 931 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 931 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:94 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 930 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 930 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 930 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 930 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 930 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:95 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 929 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 929 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 929 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 929 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 929 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:96 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 928 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 928 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 928 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 928 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 928 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:97 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 927 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 927 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 927 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 927 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 927 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:98 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 926 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 926 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 926 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 926 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 926 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:99 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 925 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 925 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 925 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 925 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 925 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:100 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 924 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 924 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 924 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 924 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 924 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:101 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 923 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 923 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 923 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 923 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 923 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:102 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 922 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 922 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 922 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 922 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 922 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:103 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 921 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 921 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 921 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 921 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 921 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:104 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 920 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 920 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 920 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 920 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 920 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:105 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 919 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 919 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 919 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 919 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 919 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:106 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 918 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 918 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 918 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 918 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 918 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:107 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 917 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 917 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 917 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 917 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 917 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:108 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 916 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 916 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 916 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 916 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 916 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:109 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 915 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 915 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 915 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 915 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 915 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:110 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 914 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 914 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 914 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 914 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 914 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:111 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 913 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 913 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 913 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 913 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 913 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:112 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 912 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 912 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 912 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 912 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 912 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:113 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 911 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 911 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 911 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 911 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 911 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:114 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 910 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 910 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 910 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 910 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 910 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:115 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 909 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 909 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 909 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 909 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 909 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:116 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 908 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 908 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 908 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 908 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 908 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:117 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 907 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 907 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 907 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 907 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 907 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:118 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 906 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 906 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 906 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 906 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 906 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:119 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 905 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 905 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 905 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 905 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 905 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:120 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 904 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 904 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 904 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 904 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 904 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:121 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 903 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 903 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 903 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 903 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 903 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:122 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 902 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 902 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 902 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 902 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 902 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:123 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 901 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 901 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 901 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 901 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 901 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:124 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 900 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 900 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 900 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 900 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 900 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:125 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 899 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 899 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 899 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 899 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 899 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:126 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 898 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 898 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 898 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 898 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 898 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:127 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 897 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 897 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 897 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 897 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 897 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:128 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 896 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 896 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 896 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 896 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 896 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:129 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 895 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 895 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 895 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 895 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 895 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:130 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 894 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 894 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 894 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 894 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 894 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:131 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 893 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 893 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 893 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 893 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 893 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:132 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 892 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 892 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 892 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 892 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 892 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:133 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 891 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 891 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 891 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 891 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 891 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:134 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 890 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 890 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 890 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 890 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 890 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:135 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 889 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 889 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 889 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 889 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 889 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:136 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 888 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 888 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 888 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 888 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 888 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:137 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 887 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 887 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 887 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 887 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 887 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:138 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 886 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 886 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 886 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 886 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 886 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:139 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 885 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 885 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 885 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 885 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 885 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:140 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 884 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 884 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 884 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 884 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 884 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:141 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 883 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 883 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 883 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 883 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 883 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:142 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 882 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 882 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 882 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 882 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 882 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:143 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 881 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 881 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 881 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 881 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 881 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:144 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 880 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 880 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 880 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 880 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 880 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 880 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:145 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 879 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 879 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 879 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 879 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 879 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 879 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:146 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 878 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 878 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 878 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 878 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 878 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 878 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:147 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 877 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 877 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 877 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 877 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 877 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 877 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:148 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 876 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 876 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 876 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 876 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 876 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 876 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:149 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 875 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 875 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 875 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 875 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 875 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 875 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:150 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 874 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 874 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 874 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 874 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 874 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 874 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:151 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 873 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 873 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 873 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 873 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 873 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 873 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:152 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 872 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 872 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 872 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 872 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 872 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 872 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:153 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 871 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 871 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 871 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 871 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 871 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:154 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 870 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 870 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 870 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 870 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 870 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:155 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 869 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 869 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 869 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 869 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 869 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:156 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 868 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 868 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 868 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 868 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 868 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:157 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 867 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 867 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 867 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 867 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 867 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:158 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 866 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 866 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 866 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 866 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 866 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:159 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 865 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 865 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 865 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 865 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 865 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:160 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 864 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 864 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 864 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 864 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 864 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:161 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 863 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 863 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 863 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 863 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 863 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:162 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 862 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 862 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 862 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 862 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 862 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:163 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 861 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 861 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 861 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 861 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 861 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:164 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 860 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 860 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 860 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 860 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 860 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:165 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 859 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 859 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 859 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 859 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 859 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:166 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 858 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 858 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 858 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 858 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 858 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:167 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 857 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 857 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 857 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 857 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 857 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:168 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 856 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 856 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 856 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 856 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 856 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:169 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 855 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 855 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 855 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 855 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 855 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:170 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 854 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 854 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 854 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 854 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 854 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:171 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 853 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 853 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 853 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 853 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 853 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:172 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 852 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 852 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 852 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 852 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 852 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:173 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 851 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 851 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 851 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 851 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 851 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:174 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 850 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 850 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 850 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 850 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 850 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:175 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 849 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 849 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 849 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 849 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 849 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:176 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 848 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 848 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 848 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 848 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 848 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:177 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 847 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 847 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 847 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 847 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 847 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:178 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 846 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 846 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 846 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 846 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 846 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:179 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 845 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 845 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 845 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 845 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 845 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:180 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 844 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 844 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 844 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 844 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 844 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:181 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 843 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 843 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 843 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 843 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 843 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:182 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 842 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 842 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 842 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 842 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 842 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:183 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 841 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 841 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 841 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 841 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 841 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:184 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 840 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 840 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 840 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 840 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 840 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:185 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 839 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 839 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 839 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 839 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 839 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:186 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 838 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 838 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 838 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 838 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 838 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:187 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 837 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 837 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 837 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 837 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 837 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:188 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 836 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 836 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 836 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 836 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 836 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:189 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 835 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 835 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 835 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 835 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 835 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:190 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 834 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 834 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 834 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 834 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 834 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:191 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 833 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 833 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 833 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 833 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 833 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:192 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 832 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 832 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 832 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 832 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 832 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:193 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 831 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 831 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 831 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 831 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 831 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:194 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 830 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 830 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 830 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 830 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 830 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:195 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 829 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 829 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 829 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 829 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 829 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:196 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 828 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 828 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 828 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 828 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 828 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:197 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 827 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 827 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 827 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 827 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 827 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:198 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 826 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 826 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 826 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 826 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 826 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:199 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 825 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 825 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 825 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 825 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 825 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:200 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 824 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 824 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 824 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 824 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 824 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:201 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 823 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 823 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 823 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 823 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 823 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:202 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 822 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 822 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 822 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 822 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 822 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:203 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 821 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 821 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 821 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 821 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 821 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:204 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 820 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 820 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 820 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 820 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 820 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:205 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 819 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 819 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 819 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 819 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 819 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:206 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 818 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 818 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 818 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 818 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 818 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:207 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 817 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 817 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 817 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 817 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 817 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:208 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 816 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 816 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 816 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 816 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 816 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:209 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 815 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 815 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 815 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 815 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 815 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:210 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 814 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 814 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 814 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 814 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 814 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:211 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 813 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 813 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 813 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 813 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 813 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:212 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 812 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 812 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 812 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 812 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 812 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:213 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 811 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 811 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 811 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 811 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 811 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:214 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 810 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 810 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 810 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 810 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 810 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:215 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 809 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 809 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 809 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 809 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 809 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:216 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 808 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 808 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 808 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 808 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 808 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 808 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:217 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 807 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 807 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 807 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 807 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 807 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 807 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:218 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 806 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 806 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 806 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 806 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 806 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 806 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:219 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 805 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 805 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 805 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 805 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 805 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 805 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:220 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 804 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 804 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 804 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 804 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 804 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 804 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:221 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 803 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 803 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 803 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 803 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 803 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 803 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:222 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 802 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 802 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 802 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 802 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 802 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 802 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:223 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 801 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 801 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 801 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 801 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 801 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 801 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:224 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 800 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 800 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 800 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 800 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 800 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 800 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:225 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 799 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 799 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 799 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 799 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 799 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:226 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 798 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 798 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 798 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 798 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 798 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:227 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 797 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 797 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 797 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 797 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 797 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:228 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 796 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 796 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 796 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 796 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 796 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:229 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 795 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 795 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 795 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 795 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 795 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:230 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 794 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 794 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 794 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 794 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 794 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:231 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 793 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 793 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 793 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 793 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 793 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:232 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 792 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 792 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 792 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 792 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 792 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:233 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 791 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 791 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 791 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 791 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 791 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:234 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 790 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 790 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 790 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 790 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 790 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:235 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 789 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 789 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 789 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 789 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 789 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:236 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 788 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 788 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 788 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 788 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 788 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:237 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 787 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 787 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 787 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 787 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 787 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:238 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 786 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 786 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 786 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 786 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 786 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:239 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 785 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 785 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 785 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 785 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 785 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:240 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 784 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 784 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 784 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 784 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 784 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:241 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 783 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 783 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 783 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 783 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 783 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:242 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 782 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 782 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 782 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 782 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 782 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:243 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 781 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 781 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 781 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 781 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 781 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:244 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 780 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 780 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 780 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 780 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 780 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:245 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 779 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 779 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 779 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 779 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 779 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:246 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 778 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 778 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 778 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 778 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 778 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:247 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 777 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 777 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 777 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 777 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 777 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:248 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 776 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 776 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 776 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 776 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 776 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:249 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 775 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 775 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 775 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 775 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 775 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:250 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 774 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 774 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 774 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 774 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 774 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:251 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 773 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 773 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 773 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 773 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 773 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:252 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 772 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 772 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 772 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 772 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 772 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:253 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 771 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 771 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 771 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 771 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 771 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:254 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 770 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 770 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 770 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 770 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 770 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:255 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 769 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 769 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 769 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 769 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 769 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:256 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 768 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 768 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 768 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 768 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 768 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:257 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 767 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 767 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 767 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 767 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 767 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:258 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 766 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 766 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 766 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 766 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 766 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:259 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 765 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 765 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 765 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 765 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 765 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:260 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 764 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 764 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 764 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 764 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 764 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:261 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 763 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 763 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 763 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 763 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 763 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:262 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 762 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 762 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 762 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 762 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 762 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:263 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 761 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 761 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 761 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 761 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 761 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:264 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 760 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 760 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 760 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 760 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 760 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:265 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 759 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 759 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 759 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 759 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 759 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:266 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 758 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 758 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 758 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 758 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 758 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:267 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 757 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 757 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 757 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 757 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 757 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:268 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 756 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 756 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 756 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 756 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 756 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:269 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 755 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 755 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 755 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 755 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 755 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:270 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 754 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 754 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 754 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 754 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 754 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:271 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 753 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 753 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 753 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 753 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 753 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:272 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 752 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 752 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 752 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 752 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 752 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:273 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 751 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 751 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 751 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 751 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 751 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:274 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 750 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 750 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 750 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 750 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 750 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:275 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 749 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 749 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 749 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 749 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 749 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:276 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 748 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 748 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 748 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 748 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 748 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:277 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 747 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 747 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 747 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 747 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 747 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:278 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 746 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 746 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 746 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 746 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 746 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:279 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 745 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 745 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 745 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 745 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 745 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:280 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 744 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 744 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 744 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 744 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 744 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:281 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 743 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 743 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 743 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 743 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 743 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:282 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 742 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 742 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 742 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 742 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 742 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:283 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 741 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 741 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 741 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 741 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 741 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:284 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 740 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 740 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 740 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 740 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 740 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:285 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 739 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 739 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 739 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 739 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 739 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:286 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 738 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 738 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 738 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 738 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 738 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:287 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 737 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 737 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 737 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 737 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] dreg_r: 00 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 737 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:288 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 736 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 736 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 736 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 736 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 736 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 736 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:289 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 735 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 735 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 735 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 735 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 735 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 735 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:290 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 734 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 734 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 734 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 734 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 734 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 734 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:291 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 733 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 733 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 733 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 733 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 733 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 733 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:292 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 732 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 732 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 732 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 732 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 732 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 732 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:293 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 731 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 731 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 731 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 731 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 731 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 731 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:294 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 730 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 730 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 730 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 730 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 730 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 730 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:295 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 729 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 729 [:exp1:cz6bs1:scsi:7:spc] pushing read data: 00 [:exp1:cz6bs1:scsi:7:spc] Calling m_dreq_handler(true) [:exp1:cz6bs1:scsi:7:spc] new state: TransferRecvData -> TransferSendAck (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 29 TC 729 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 49 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferSendAck, data 00 ctrl 49 TC 729 [:exp1:cz6bs1:scsi:7:spc] new state: TransferSendAck -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferWaitDeassertREQ (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitDeassertREQ, data 00 ctrl 49 TC 729 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitDeassertREQ -> TransferDeassertACK (delay 10, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferDeassertACK, data 00 ctrl 49 TC 729 [:exp1:cz6bs1:scsi:7:spc] new state: TransferDeassertACK -> TransferWaitReq (delay 10, timeout 0) [:exp1:cz6bs1:scsi:0:harddisk] nscsi_hd: scsi_get_data, id:2 pos:296 data:00 [:exp1:cz6bs1:scsi:7:spc] scsi_ctrl_changed: 29 [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferWaitReq, data 00 ctrl 29 TC 728 [:exp1:cz6bs1:scsi:7:spc] new state: TransferWaitReq -> TransferRecvData (delay 1, timeout 0) [:exp1:cz6bs1:scsi:7:spc] step: 1 TransferRecvData, data 00 ctrl 29 TC 728 [:keyboard:x68k] KB: LED status set to 6f | |||||
reverted-mb89352-error.log.txt (173,820 bytes) Jan 5, 2024, 11:30 Uploaded by grantek Verbose log from MAME HEAD with mb89352.cpp restored and hooked up [Show Content] [Hide Content]Soft reset [:exp1:cz6bs1:scsi:2:harddisk] T10SBC :exp1:cz6bs1:scsi:2:harddisk: no HD found! [:exp1:cz6bs1:scsi:3:harddisk] T10SBC :exp1:cz6bs1:scsi:3:harddisk: no HD found! [:exp1:cz6bs1:scsi:4:harddisk] T10SBC :exp1:cz6bs1:scsi:4:harddisk: no HD found! [:exp1:cz6bs1:scsi:5:harddisk] T10SBC :exp1:cz6bs1:scsi:5:harddisk: no HD found! [:exp1:cz6bs1:scsi:6:harddisk] T10SBC :exp1:cz6bs1:scsi:6:harddisk: no HD found! [:exp1:cz6bs1:scsi:7:harddisk] T10SBC :exp1:cz6bs1:scsi:7:harddisk: no HD found! [:crtc] visarea larger then reg[20]: 992x551, 0x0 [:crtc] visarea larger then reg[20]: 992x551, 0x0 [:crtc] visarea larger then reg[20]: 992x551, 0x0 [:crtc] visarea larger then reg[20]: 992x551, 0x0 [:crtc] visarea larger then reg[20]: 992x551, 0x0 [:crtc] visarea larger then reg[20]: 992x551, 0x0 [:crtc] visarea larger then reg[20]: 992x551, 0x0 [:crtc] visarea larger then reg[20]: 992x551, 0x0 [:crtc] visarea larger then reg[20]: 992x551, 0x0 [:crtc] CRTC: Register 20 = 0316 [:crtc] visarea larger then reg[20]: 992x551, 768x512 [:crtc] CRTC: Register 20 = 0b16 [:crtc] visarea larger then reg[20]: 992x551, 768x512 [:keyboard:x68k] KB: LED status set to 7f [:keyboard:x68k] KB: LED status set to 7f [:keyboard:x68k] KB: Keyboard enable bit = 1 [:keyboard:x68k] KB: Keypress delay time is now 500ms [:keyboard:x68k] KB: Keypress repeat rate is now 30ms [:maincpu] ':maincpu' (FF8190): unmapped program memory write to E8C002 = 0101 & 00FF [:keyboard:x68k] KB: LED status set to 6f [:x68k_hdc] SASI: SPECIFY [:x68k_hdc] SPECIFY: wrote 0x101 [:x68k_hdc] SPECIFY: wrote 0x101 [:x68k_hdc] SPECIFY: wrote 0x00 [:x68k_hdc] SPECIFY: wrote 0x303 [:x68k_hdc] SPECIFY: wrote 0x202 [:x68k_hdc] SPECIFY: wrote 0x9898 [:x68k_hdc] SPECIFY: wrote 0x8080 [:x68k_hdc] SPECIFY: wrote 0x00 [:x68k_hdc] SPECIFY: wrote 0x00 [:x68k_hdc] SPECIFY: wrote 0x00 [:x68k_hdc] SASI: Write transfer complete [:x68k_hdc] SASI: No HD connected [:x68k_hdc] SASI: REQUEST SENSE [:x68k_hdc] REQUEST SENSE: read value 0x01 [:x68k_hdc] REQUEST SENSE: read value 0x00 [:x68k_hdc] REQUEST SENSE: read value 0x00 [:x68k_hdc] REQUEST SENSE: read value 0x00 [:x68k_hdc] SASI: Read transfer complete [:crtc] visarea larger then reg[20]: 992x551, 768x512 [:crtc] visarea larger then reg[20]: 992x551, 768x512 [:crtc] visarea larger then reg[20]: 992x551, 768x512 [:crtc] visarea larger then reg[20]: 992x551, 768x512 [:crtc] visarea larger then reg[20]: 992x551, 768x512 [:crtc] visarea larger then reg[20]: 992x551, 768x512 [:crtc] visarea larger then reg[20]: 992x551, 768x512 [:crtc] visarea larger then reg[20]: 992x551, 768x512 [:crtc] visarea larger then reg[20]: 992x551, 768x512 [:crtc] CRTC: Register 20 = 0316 [:crtc] visarea larger then reg[20]: 992x551, 768x512 [:crtc] CRTC: Register 20 = 0b16 [:crtc] visarea larger then reg[20]: 992x551, 768x512 [:maincpu] ':maincpu' (FF8190): unmapped program memory write to E8C002 = 0101 & 00FF [:maincpu] ':maincpu' (FF8190): unmapped program memory write to E8C002 = 0101 & 00FF [:x68k_hdc] SASI: SPECIFY [:x68k_hdc] SPECIFY: wrote 0x101 [:x68k_hdc] SPECIFY: wrote 0x101 [:x68k_hdc] SPECIFY: wrote 0x00 [:x68k_hdc] SPECIFY: wrote 0x303 [:x68k_hdc] SPECIFY: wrote 0x202 [:x68k_hdc] SPECIFY: wrote 0x9898 [:x68k_hdc] SPECIFY: wrote 0x8080 [:x68k_hdc] SPECIFY: wrote 0x00 [:x68k_hdc] SPECIFY: wrote 0x00 [:x68k_hdc] SPECIFY: wrote 0x00 [:x68k_hdc] SASI: Write transfer complete [:x68k_hdc] SASI: No HD connected [:x68k_hdc] SASI: REQUEST SENSE [:x68k_hdc] REQUEST SENSE: read value 0x01 [:x68k_hdc] REQUEST SENSE: read value 0x00 [:x68k_hdc] REQUEST SENSE: read value 0x00 [:x68k_hdc] REQUEST SENSE: read value 0x00 [:x68k_hdc] SASI: Read transfer complete [:x68k_hdc] SASI: REZERO UNIT [:x68k_hdc] SASI: SPECIFY [:x68k_hdc] SPECIFY: wrote 0x101 [:x68k_hdc] SPECIFY: wrote 0x101 [:x68k_hdc] SPECIFY: wrote 0x00 [:x68k_hdc] SPECIFY: wrote 0x303 [:x68k_hdc] SPECIFY: wrote 0x202 [:x68k_hdc] SPECIFY: wrote 0x9898 [:x68k_hdc] SPECIFY: wrote 0x8080 [:x68k_hdc] SPECIFY: wrote 0x00 [:x68k_hdc] SPECIFY: wrote 0x00 [:x68k_hdc] SPECIFY: wrote 0x00 [:x68k_hdc] SASI: Write transfer complete [:x68k_hdc] SASI: No HD connected [:x68k_hdc] SASI: REQUEST SENSE [:x68k_hdc] REQUEST SENSE: read value 0x01 [:x68k_hdc] REQUEST SENSE: read value 0x00 [:x68k_hdc] REQUEST SENSE: read value 0x00 [:x68k_hdc] REQUEST SENSE: read value 0x00 [:x68k_hdc] SASI: Read transfer complete [:x68k_hdc] SASI: No HD connected [:x68k_hdc] SASI: REQUEST SENSE [:x68k_hdc] REQUEST SENSE: read value 0x01 [:x68k_hdc] REQUEST SENSE: read value 0x00 [:x68k_hdc] REQUEST SENSE: read value 0x00 [:x68k_hdc] REQUEST SENSE: read value 0x00 [:x68k_hdc] SASI: Read transfer complete [:x68k_hdc] SASI: SPECIFY [:x68k_hdc] SPECIFY: wrote 0x101 [:x68k_hdc] SPECIFY: wrote 0x101 [:x68k_hdc] SPECIFY: wrote 0x00 [:x68k_hdc] SPECIFY: wrote 0x303 [:x68k_hdc] SPECIFY: wrote 0x202 [:x68k_hdc] SPECIFY: wrote 0x9898 [:x68k_hdc] SPECIFY: wrote 0x8080 [:x68k_hdc] SPECIFY: wrote 0x00 [:x68k_hdc] SPECIFY: wrote 0x00 [:x68k_hdc] SPECIFY: wrote 0x00 [:x68k_hdc] SASI: Write transfer complete [:x68k_hdc] SASI: No HD connected [:x68k_hdc] SASI: REQUEST SENSE [:x68k_hdc] REQUEST SENSE: read value 0x01 [:x68k_hdc] REQUEST SENSE: read value 0x00 [:x68k_hdc] REQUEST SENSE: read value 0x00 [:x68k_hdc] REQUEST SENSE: read value 0x00 [:x68k_hdc] SASI: Read transfer complete [:x68k_hdc] SASI: REZERO UNIT [:exp1:cz6bs1:mb89352] mb89352: SCTL: Reset and disable. [:exp1:cz6bs1:mb89352] mb89352: SCTL: Arbitration enabled. [:exp1:cz6bs1:mb89352] mb89352: SCTL: Interrupts disabled. [:exp1:cz6bs1:mb89352] mb89352: BDID set to 0x07 [:exp1:cz6bs1:mb89352] MB89352: phase set to 0x08 [:exp1:cz6bs1:mb89352] mb89352: SCMD: Bus free [:exp1:cz6bs1:mb89352] mb89352: PCTL write 00 [:exp1:cz6bs1:mb89352] mb89352: TCH: Write 00 [000000] [:exp1:cz6bs1:mb89352] mb89352: TCM: Write 00 [000000] [:exp1:cz6bs1:mb89352] mb89352: TCL: Write 00 [000000] [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCTL: Arbitration enabled. [:exp1:cz6bs1:mb89352] mb89352: SCTL: Interrupts disabled. [:exp1:cz6bs1:mb89352] mb89352: write 00 to register 05 [:exp1:cz6bs1:mb89352] MB89352: phase set to 0x08 [:exp1:cz6bs1:mb89352] mb89352: SCMD: Bus free [:exp1:cz6bs1:mb89352] MB89352: phase set to 0x08 [:exp1:cz6bs1:mb89352] mb89352: SCMD: Bus free [:exp1:cz6bs1:mb89352] mb89352: PCTL write 00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0x05 [:exp1:cz6bs1:mb89352] mb89352_r: BDID 0x80 [:exp1:cz6bs1:mb89352] mb89352: SCTL: Arbitration enabled. [:exp1:cz6bs1:mb89352] mb89352: SCTL: Interrupts disabled. [:exp1:cz6bs1:mb89352] mb89352: Write 80 to temporary register [:exp1:cz6bs1:mb89352] mb89352: TCM: Write c4 [00c400] [:exp1:cz6bs1:mb89352] mb89352: TCH: Write 09 [09c400] [:exp1:cz6bs1:mb89352] mb89352: TCL: Write 03 [09c403] [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352: Reset INTS status bits 00 [:exp1:cz6bs1:mb89352] MB89352: phase set to 0x02 [:exp1:cz6bs1:mb89352] mb89352: SCMD: Selection (SCSI ID0) [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x10 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x10 [:exp1:cz6bs1:mb89352] mb89352: Reset INTS status bits 10 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:scsi:1:harddisk] T10SPC: TEST UNIT READY [:exp1:cz6bs1:mb89352] MB89352: phase set to 0x03 [:exp1:cz6bs1:mb89352] Command executed: [:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5b [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9b [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9b [:exp1:cz6bs1:mb89352] mb89352: PCTL write 03 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9b [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] MB89352: phase set to 0x07 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5f [:exp1:cz6bs1:mb89352] mb89352_r: TEMP 0x00 [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9f [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9f [:exp1:cz6bs1:mb89352] mb89352: PCTL write 07 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9f [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] MB89352: phase set to 0x08 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: TEMP 0x00 [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352: PCTL write 00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0x01 [:exp1:cz6bs1:mb89352] mb89352_r: BDID 0x80 [:exp1:cz6bs1:mb89352] mb89352: SCTL: Arbitration enabled. [:exp1:cz6bs1:mb89352] mb89352: SCTL: Interrupts disabled. [:exp1:cz6bs1:mb89352] mb89352: Write 81 to temporary register [:exp1:cz6bs1:mb89352] mb89352: TCM: Write c4 [09c403] [:exp1:cz6bs1:mb89352] mb89352: TCH: Write 09 [09c403] [:exp1:cz6bs1:mb89352] mb89352: TCL: Write 03 [09c403] [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352: Reset INTS status bits 00 [:exp1:cz6bs1:mb89352] MB89352: phase set to 0x02 [:exp1:cz6bs1:mb89352] mb89352: SCMD: Selection (SCSI ID0) [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x10 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x10 [:exp1:cz6bs1:mb89352] mb89352: Reset INTS status bits 10 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:scsi:1:harddisk] T10SPC: TEST UNIT READY [:exp1:cz6bs1:mb89352] MB89352: phase set to 0x03 [:exp1:cz6bs1:mb89352] Command executed: [:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5b [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9b [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9b [:exp1:cz6bs1:mb89352] mb89352: PCTL write 03 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9b [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] MB89352: phase set to 0x07 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5f [:exp1:cz6bs1:mb89352] mb89352_r: TEMP 0x00 [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9f [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9f [:exp1:cz6bs1:mb89352] mb89352: PCTL write 07 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9f [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] MB89352: phase set to 0x08 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: TEMP 0x00 [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352: PCTL write 00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0x01 [:exp1:cz6bs1:mb89352] mb89352_r: BDID 0x80 [:exp1:cz6bs1:mb89352] mb89352: SCTL: Arbitration enabled. [:exp1:cz6bs1:mb89352] mb89352: SCTL: Interrupts disabled. [:exp1:cz6bs1:mb89352] mb89352: Write 81 to temporary register [:exp1:cz6bs1:mb89352] mb89352: TCM: Write c4 [09c403] [:exp1:cz6bs1:mb89352] mb89352: TCH: Write 09 [09c403] [:exp1:cz6bs1:mb89352] mb89352: TCL: Write 03 [09c403] [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352: Reset INTS status bits 00 [:exp1:cz6bs1:mb89352] MB89352: phase set to 0x02 [:exp1:cz6bs1:mb89352] mb89352: SCMD: Selection (SCSI ID0) [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x10 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x10 [:exp1:cz6bs1:mb89352] mb89352: Reset INTS status bits 10 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 12 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 20 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:scsi:1:harddisk] T10SBC: INQUIRY [:exp1:cz6bs1:mb89352] MB89352: phase set to 0x01 [:exp1:cz6bs1:mb89352] Command executed: [:exp1:cz6bs1:mb89352] 12[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] 20[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x59 [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x99 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x99 [:exp1:cz6bs1:mb89352] mb89352: PCTL write 01 [:exp1:cz6bs1:mb89352] mb89352: TCL: Write 20 [09c420] [:exp1:cz6bs1:mb89352] mb89352: TCM: Write 00 [090020] [:exp1:cz6bs1:mb89352] mb89352: TCH: Write 00 [000020] [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352: Reset INTS status bits 00 [:exp1:cz6bs1:mb89352] mb89352: SCMD: xfer data-in [:exp1:cz6bs1:mb89352] mb89352: SCMD: Start Transfer 01 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x05 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x02 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x53 S [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x45 E [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x41 A [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x47 G [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x41 A [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x54 T [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x45 E [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x53 S [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x54 T [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x32 2 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x32 2 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x35 5 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] MB89352: phase set to 0x03 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x4e N [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x10 [:exp1:cz6bs1:mb89352] mb89352: Reset INTS status bits 10 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9b [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9b [:exp1:cz6bs1:mb89352] mb89352: PCTL write 03 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9b [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] MB89352: phase set to 0x07 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5f [:exp1:cz6bs1:mb89352] mb89352_r: TEMP 0x00 [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9f [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9f [:exp1:cz6bs1:mb89352] mb89352: PCTL write 07 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9f [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] MB89352: phase set to 0x08 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: TEMP 0x00 [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352: PCTL write 00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0x01 [:exp1:cz6bs1:mb89352] mb89352_r: BDID 0x80 [:exp1:cz6bs1:mb89352] mb89352: SCTL: Arbitration enabled. [:exp1:cz6bs1:mb89352] mb89352: SCTL: Interrupts disabled. [:exp1:cz6bs1:mb89352] mb89352: Write 81 to temporary register [:exp1:cz6bs1:mb89352] mb89352: TCM: Write c4 [00c400] [:exp1:cz6bs1:mb89352] mb89352: TCH: Write 09 [09c400] [:exp1:cz6bs1:mb89352] mb89352: TCL: Write 03 [09c403] [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352: Reset INTS status bits 00 [:exp1:cz6bs1:mb89352] MB89352: phase set to 0x02 [:exp1:cz6bs1:mb89352] mb89352: SCMD: Selection (SCSI ID0) [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x10 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x10 [:exp1:cz6bs1:mb89352] mb89352: Reset INTS status bits 10 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 25 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:scsi:1:harddisk] T10SBC: READ CAPACITY [:exp1:cz6bs1:mb89352] MB89352: phase set to 0x01 [:exp1:cz6bs1:mb89352] Command executed: [:exp1:cz6bs1:mb89352] 25[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x59 [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x99 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x99 [:exp1:cz6bs1:mb89352] mb89352: PCTL write 01 [:exp1:cz6bs1:mb89352] mb89352: TCL: Write 08 [09c408] [:exp1:cz6bs1:mb89352] mb89352: TCM: Write 00 [090008] [:exp1:cz6bs1:mb89352] mb89352: TCH: Write 00 [000008] [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352: Reset INTS status bits 00 [:exp1:cz6bs1:mb89352] mb89352: SCMD: xfer data-in [:exp1:cz6bs1:scsi:1:harddisk] T10SBC: READ CAPACITY [:exp1:cz6bs1:mb89352] mb89352: SCMD: Start Transfer 01 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x18 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x49 I [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x4f O [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x02 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] MB89352: phase set to 0x03 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x10 [:exp1:cz6bs1:mb89352] mb89352: Reset INTS status bits 10 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9b [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9b [:exp1:cz6bs1:mb89352] mb89352: PCTL write 03 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9b [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] MB89352: phase set to 0x07 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5f [:exp1:cz6bs1:mb89352] mb89352_r: TEMP 0x00 [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9f [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9f [:exp1:cz6bs1:mb89352] mb89352: PCTL write 07 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9f [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] MB89352: phase set to 0x08 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: TEMP 0x00 [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352: PCTL write 00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0x01 [:exp1:cz6bs1:mb89352] mb89352_r: BDID 0x80 [:exp1:cz6bs1:mb89352] mb89352: SCTL: Arbitration enabled. [:exp1:cz6bs1:mb89352] mb89352: SCTL: Interrupts disabled. [:exp1:cz6bs1:mb89352] mb89352: Write 81 to temporary register [:exp1:cz6bs1:mb89352] mb89352: TCM: Write c4 [00c400] [:exp1:cz6bs1:mb89352] mb89352: TCH: Write 09 [09c400] [:exp1:cz6bs1:mb89352] mb89352: TCL: Write 03 [09c403] [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352: Reset INTS status bits 00 [:exp1:cz6bs1:mb89352] MB89352: phase set to 0x02 [:exp1:cz6bs1:mb89352] mb89352: SCMD: Selection (SCSI ID0) [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x10 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x10 [:exp1:cz6bs1:mb89352] mb89352: Reset INTS status bits 10 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 08 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 01 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:scsi:1:harddisk] T10SBC: READ at LBA 0 for 1 blocks [:exp1:cz6bs1:mb89352] MB89352: phase set to 0x01 [:exp1:cz6bs1:mb89352] Command executed: [:exp1:cz6bs1:mb89352] 08[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] 01[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x59 [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x99 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x99 [:exp1:cz6bs1:mb89352] mb89352: PCTL write 01 [:exp1:cz6bs1:mb89352] mb89352: TCL: Write 00 [09c400] [:exp1:cz6bs1:mb89352] mb89352: TCM: Write 02 [090200] [:exp1:cz6bs1:mb89352] mb89352: TCH: Write 00 [000200] [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352: Reset INTS status bits 00 [:exp1:cz6bs1:mb89352] mb89352: SCMD: xfer data-in [:exp1:cz6bs1:scsi:1:harddisk] T10SBC: Reading 512 bytes from HD [:exp1:cz6bs1:mb89352] mb89352: SCMD: Start Transfer 01 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x58 X [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x36 6 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x38 8 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x53 S [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x43 C [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x53 S [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x49 I [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x31 1 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x02 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x0c [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x24 $ [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xa7 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x01 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x54 T [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x68 h [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x69 i [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x73 s [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x53 S [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x43 C [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x53 S [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x49 I [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x2d - [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x55 U [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x4e N [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x49 I [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x54 T [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x66 f [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x6f o [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x72 r [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x6d m [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x61 a [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x74 t [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x69 i [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x73 s [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x27 ' [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x53 S [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x78 x [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x53 S [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x49 I [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x27 ' [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x66 f [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x6f o [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x72 r [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x73 s [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x63 c [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x73 s [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x69 i [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x66 f [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x6f o [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x72 r [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x6d m [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x2e . [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x62 b [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x79 y [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x48 H [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x65 e [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x72 r [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x6f o [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x53 S [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x6f o [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x66 f [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x74 t [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x2e . [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x28 ( [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x43 C [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x2d - [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x6c l [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x61 a [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x62 b [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x43 C [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x4f O [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x29 ) [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] MB89352: phase set to 0x03 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x10 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x10 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x10 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x10 [:exp1:cz6bs1:mb89352] mb89352: Reset INTS status bits 10 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9b [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9b [:exp1:cz6bs1:mb89352] mb89352: PCTL write 03 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9b [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] MB89352: phase set to 0x07 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5f [:exp1:cz6bs1:mb89352] mb89352_r: TEMP 0x00 [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9f [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9f [:exp1:cz6bs1:mb89352] mb89352: PCTL write 07 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9f [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] MB89352: phase set to 0x08 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: TEMP 0x00 [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352: PCTL write 00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0x01 [:exp1:cz6bs1:mb89352] mb89352_r: BDID 0x80 [:exp1:cz6bs1:mb89352] mb89352: SCTL: Arbitration enabled. [:exp1:cz6bs1:mb89352] mb89352: SCTL: Interrupts disabled. [:exp1:cz6bs1:mb89352] mb89352: Write 81 to temporary register [:exp1:cz6bs1:mb89352] mb89352: TCM: Write c4 [00c400] [:exp1:cz6bs1:mb89352] mb89352: TCH: Write 09 [09c400] [:exp1:cz6bs1:mb89352] mb89352: TCL: Write 03 [09c403] [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352: Reset INTS status bits 00 [:exp1:cz6bs1:mb89352] MB89352: phase set to 0x02 [:exp1:cz6bs1:mb89352] mb89352: SCMD: Selection (SCSI ID0) [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x10 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x10 [:exp1:cz6bs1:mb89352] mb89352: Reset INTS status bits 10 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 08 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 04 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 01 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:scsi:1:harddisk] T10SBC: READ at LBA 4 for 1 blocks [:exp1:cz6bs1:mb89352] MB89352: phase set to 0x01 [:exp1:cz6bs1:mb89352] Command executed: [:exp1:cz6bs1:mb89352] 08[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] 04[:exp1:cz6bs1:mb89352] 01[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x59 [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x99 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x99 [:exp1:cz6bs1:mb89352] mb89352: PCTL write 01 [:exp1:cz6bs1:mb89352] mb89352: TCL: Write 00 [09c400] [:exp1:cz6bs1:mb89352] mb89352: TCM: Write 02 [090200] [:exp1:cz6bs1:mb89352] mb89352: TCH: Write 00 [000200] [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352: Reset INTS status bits 00 [:exp1:cz6bs1:mb89352] mb89352: SCMD: xfer data-in [:exp1:cz6bs1:scsi:1:harddisk] T10SBC: Reading 512 bytes from HD [:exp1:cz6bs1:mb89352] mb89352: SCMD: Start Transfer 01 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x58 X [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x36 6 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x38 8 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x4b K [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x0c [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x24 $ [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xa7 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x0c [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x24 $ [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xa7 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x0c [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x24 $ [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xa7 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x48 H [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x75 u [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x6d m [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x61 a [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x6e n [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x36 6 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x38 8 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x6b k [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x0c [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x24 $ [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x87 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] MB89352: phase set to 0x03 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x10 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x10 [:exp1:cz6bs1:mb89352] mb89352: Reset INTS status bits 10 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9b [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9b [:exp1:cz6bs1:mb89352] mb89352: PCTL write 03 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9b [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] MB89352: phase set to 0x07 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5f [:exp1:cz6bs1:mb89352] mb89352_r: TEMP 0x00 [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9f [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9f [:exp1:cz6bs1:mb89352] mb89352: PCTL write 07 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9f [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] MB89352: phase set to 0x08 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: TEMP 0x00 [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352: PCTL write 00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0x01 [:exp1:cz6bs1:mb89352] mb89352_r: BDID 0x80 [:exp1:cz6bs1:mb89352] mb89352: SCTL: Arbitration enabled. [:exp1:cz6bs1:mb89352] mb89352: SCTL: Interrupts disabled. [:exp1:cz6bs1:mb89352] mb89352: Write 81 to temporary register [:exp1:cz6bs1:mb89352] mb89352: TCM: Write c4 [00c400] [:exp1:cz6bs1:mb89352] mb89352: TCH: Write 09 [09c400] [:exp1:cz6bs1:mb89352] mb89352: TCL: Write 03 [09c403] [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352: Reset INTS status bits 00 [:exp1:cz6bs1:mb89352] MB89352: phase set to 0x02 [:exp1:cz6bs1:mb89352] mb89352: SCMD: Selection (SCSI ID0) [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x10 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x10 [:exp1:cz6bs1:mb89352] mb89352: Reset INTS status bits 10 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 28 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 40 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 01 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5a [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: PCTL write 02 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9a [:exp1:cz6bs1:mb89352] mb89352: Write 00 to temporary register [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:scsi:1:harddisk] T10SBC: READ at LBA 40 for 1 blocks [:exp1:cz6bs1:mb89352] MB89352: phase set to 0x01 [:exp1:cz6bs1:mb89352] Command executed: [:exp1:cz6bs1:mb89352] 28[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] 40[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] 01[:exp1:cz6bs1:mb89352] 00[:exp1:cz6bs1:mb89352] [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x59 [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x99 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x99 [:exp1:cz6bs1:mb89352] mb89352: PCTL write 01 [:exp1:cz6bs1:mb89352] mb89352: TCL: Write 00 [09c400] [:exp1:cz6bs1:mb89352] mb89352: TCM: Write 02 [090200] [:exp1:cz6bs1:mb89352] mb89352: TCH: Write 00 [000200] [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352: Reset INTS status bits 00 [:exp1:cz6bs1:mb89352] mb89352: SCMD: xfer data-in [:exp1:cz6bs1:scsi:1:harddisk] T10SBC: Reading 512 bytes from HD [:exp1:cz6bs1:mb89352] mb89352: SCMD: Start Transfer 01 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x60 ` [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x24 $ [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x48 H [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x65 e [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x72 r [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x6f o [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x53 S [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x6f o [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x66 f [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x74 t [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x56 V [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x31 1 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x2e . [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x31 1 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x30 0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x04 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x10 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x02 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x01 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x04 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xf7 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x62 b [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x0c [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x24 $ [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x87 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x4f O [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xfa [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xff [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xd8 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x43 C [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xfa [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x01 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x30 0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x72 r [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x25 % [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x70 p [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xf5 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x4e N [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x4f O [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x4a J [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x66 f [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xce [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x2a * [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x29 ) [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x04 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xef [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x5d ] [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x42 B [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x40 @ [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x10 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x3a : [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xff [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xd9 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x42 B [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x42 B [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x14 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x3a : [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xff [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xcb [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xc4 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xc0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x30 0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x3a : [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xff [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xc6 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xd4 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x80 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xd4 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xba [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xff [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xcc [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x42 B [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x43 C [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x36 6 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x3a : [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xff [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xbc [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x86 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xfc [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x2c , [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x02 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xdc [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x83 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xe5 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x8a [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xea [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xaa [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xe5 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x8b [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xea [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xab [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x70 p [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xf5 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x72 r [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x26 & [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x4e N [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x4f O [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x4a J [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x80 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x66 f [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x8e [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x34 4 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x3a : [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xff [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x9c [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x53 S [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x42 B [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x41 A [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xfa [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x9c [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x30 0 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x3c < [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x0a [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x12 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x31 1 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x82 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x3c < [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xb2 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x30 0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x66 f [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x06 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x51 Q [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xc8 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xff [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xf0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x60 ` [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x0a [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x43 C [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xe9 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x51 Q [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xca [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xff [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xe2 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x60 ` [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x66 f [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x42 B [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x82 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x34 4 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x29 ) [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x1a [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xe0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x5a Z [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x55 U [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x42 B [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x42 B [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x80 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x10 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x3a : [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xff [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x60 ` [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xc4 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xc0 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xd4 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x86 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x76 v [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x01 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xe5 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x8a [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xea [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xaa [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x70 p [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xf5 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x72 r [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x26 & [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x4e N [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x4f O [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x4a J [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x80 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x66 f [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x3c < [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x0c [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x51 Q [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x48 H [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x55 U [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x66 f [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x3c < [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x0c [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xa9 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x68 h [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x04 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x66 f [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x32 2 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x26 & [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x29 ) [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x0c [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xd6 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xa9 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x10 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xd6 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xbc [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x40 @ [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xe0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x8b [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xe4 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x8b [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x52 R [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x83 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x22 " [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x7c | [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x67 g [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xc0 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xe5 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x8b [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xea [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xab [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x70 p [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xf5 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x72 r [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x26 & [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x4e N [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x4f O [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x4a J [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x80 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: SSTS 0xb0 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x66 f [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x04 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x4e N [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xe9 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x40 @ [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x43 C [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xfa [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x21 ! [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x60 ` [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x04 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x43 C [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xfa [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x27 ' [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x70 p [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x21 ! [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x4e N [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x4f O [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x43 C [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xfa [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x34 4 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x70 p [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x21 ! [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x4e N [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x4f O [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x60 ` [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0xfe [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x68 h [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x75 u [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x6d m [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x61 a [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x6e n [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x73 s [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x79 y [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x73 s [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x52 R [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x65 e [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x61 a [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x64 d [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x65 e [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x72 r [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x72 r [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x6f o [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x72 r [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x2e . [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x4e N [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x6f o [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x74 t [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x68 h [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x69 i [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x6e n [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x67 g [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x73 s [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x79 y [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x73 s [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x74 t [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x65 e [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x6d m [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x66 f [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x69 i [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x6c l [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x65 e [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x2e . [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x53 S [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x6f o [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x72 r [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x65 e [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x73 s [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x65 e [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x74 t [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x20 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x70 p [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x6c l [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x65 e [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x61 a [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x73 s [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x65 e [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x2e . [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] MB89352: phase set to 0x03 [:exp1:cz6bs1:mb89352] mb89352_r: DREG 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x10 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x10 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x10 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x10 [:exp1:cz6bs1:mb89352] mb89352: Reset INTS status bits 10 [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9b [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9b [:exp1:cz6bs1:mb89352] mb89352: PCTL write 03 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9b [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] MB89352: phase set to 0x07 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x5f [:exp1:cz6bs1:mb89352] mb89352_r: TEMP 0x00 [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:exp1:cz6bs1:mb89352] mb89352_r: INTS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9f [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9f [:exp1:cz6bs1:mb89352] mb89352: PCTL write 07 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x9f [:exp1:cz6bs1:mb89352] mb89352: SCMD: Set REQ/ACK [:exp1:cz6bs1:mb89352] MB89352: phase set to 0x08 [:exp1:cz6bs1:mb89352] mb89352_r: PSNS 0x00 [:exp1:cz6bs1:mb89352] mb89352_r: TEMP 0x00 [:exp1:cz6bs1:mb89352] mb89352: SCMD: Reset REQ/ACK [:maincpu] ':maincpu' (FF8190): unmapped program memory write to E8C002 = 0101 & 00FF [:maincpu] ':maincpu' (02D486): unmapped program memory read from EAFC04 & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC04 = 0009 & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC04 = 00C0 & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC04 = 0009 & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC04 = 0080 & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC04 = 0004 & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC04 = 0045 & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC04 = 0001 & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC04 = 0000 & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC04 = 0002 & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC04 = 00B0 & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC04 = 0003 & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC04 = 00C0 & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC04 = 0005 & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC04 = 00E2 & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC04 = 0009 & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC04 = 0001 & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC04 = 000B & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC04 = 0056 & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC04 = 000C & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC04 = 000E & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC04 = 000D & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC04 = 0000 & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC04 = 000E & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC04 = 0002 & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC04 = 0003 & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC04 = 00C1 & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC04 = 0005 & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC04 = 00EA & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC04 = 0000 & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC04 = 0080 & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC04 = 000E & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC04 = 0003 & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC04 = 000F & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC04 = 0000 & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC04 = 0000 & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC04 = 0010 & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC04 = 0000 & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC04 = 0010 & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC04 = 0001 & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC04 = 0010 & FFFF [:maincpu] ':maincpu' (02D4F4): unmapped program memory write to EAFC00 = 0009 & FFFF [:maincpu] ':maincpu' (02D502): unmapped program memory write to EAFC00 = 0040 & FFFF [:maincpu] ':maincpu' (02D4F4): unmapped program memory write to EAFC00 = 0004 & FFFF [:maincpu] ':maincpu' (02D502): unmapped program memory write to EAFC00 = 0045 & FFFF [:maincpu] ':maincpu' (02D4F4): unmapped program memory write to EAFC00 = 0001 & FFFF [:maincpu] ':maincpu' (02D502): unmapped program memory write to EAFC00 = 0000 & FFFF [:maincpu] ':maincpu' (02D4F4): unmapped program memory write to EAFC00 = 0003 & FFFF [:maincpu] ':maincpu' (02D502): unmapped program memory write to EAFC00 = 00C0 & FFFF [:maincpu] ':maincpu' (02D4F4): unmapped program memory write to EAFC00 = 0005 & FFFF [:maincpu] ':maincpu' (02D502): unmapped program memory write to EAFC00 = 0060 & FFFF [:maincpu] ':maincpu' (02D4F4): unmapped program memory write to EAFC00 = 000B & FFFF [:maincpu] ':maincpu' (02D502): unmapped program memory write to EAFC00 = 0056 & FFFF [:maincpu] ':maincpu' (02D4F4): unmapped program memory write to EAFC00 = 000C & FFFF [:maincpu] ':maincpu' (02D502): unmapped program memory write to EAFC00 = 000E & FFFF [:maincpu] ':maincpu' (02D4F4): unmapped program memory write to EAFC00 = 000D & FFFF [:maincpu] ':maincpu' (02D502): unmapped program memory write to EAFC00 = 0000 & FFFF [:maincpu] ':maincpu' (02D4F4): unmapped program memory write to EAFC00 = 000E & FFFF [:maincpu] ':maincpu' (02D502): unmapped program memory write to EAFC00 = 0002 & FFFF [:maincpu] ':maincpu' (02D4F4): unmapped program memory write to EAFC00 = 0003 & FFFF [:maincpu] ':maincpu' (02D502): unmapped program memory write to EAFC00 = 00C1 & FFFF [:maincpu] ':maincpu' (02D4F4): unmapped program memory write to EAFC00 = 0005 & FFFF [:maincpu] ':maincpu' (02D502): unmapped program memory write to EAFC00 = 00EA & FFFF [:maincpu] ':maincpu' (02D4F4): unmapped program memory write to EAFC00 = 0000 & FFFF [:maincpu] ':maincpu' (02D502): unmapped program memory write to EAFC00 = 0080 & FFFF [:maincpu] ':maincpu' (02D4F4): unmapped program memory write to EAFC00 = 000E & FFFF [:maincpu] ':maincpu' (02D502): unmapped program memory write to EAFC00 = 0003 & FFFF [:maincpu] ':maincpu' (02D4F4): unmapped program memory write to EAFC00 = 000F & FFFF [:maincpu] ':maincpu' (02D502): unmapped program memory write to EAFC00 = 0000 & FFFF [:maincpu] ':maincpu' (02D4F4): unmapped program memory write to EAFC00 = 0000 & FFFF [:maincpu] ':maincpu' (02D502): unmapped program memory write to EAFC00 = 0010 & FFFF [:maincpu] ':maincpu' (02D4F4): unmapped program memory write to EAFC00 = 0000 & FFFF [:maincpu] ':maincpu' (02D502): unmapped program memory write to EAFC00 = 0010 & FFFF [:maincpu] ':maincpu' (02D4F4): unmapped program memory write to EAFC00 = 0001 & FFFF [:maincpu] ':maincpu' (02D502): unmapped program memory write to EAFC00 = 0010 & FFFF [:maincpu] ':maincpu' (02D4F4): unmapped program memory write to EAFC00 = 0009 & FFFF [:maincpu] ':maincpu' (02D502): unmapped program memory write to EAFC00 = 0009 & FFFF [:maincpu] ':maincpu' (02D50E): unmapped program memory write to EAFC08 = 0001 & FFFF [:maincpu] ':maincpu' (02CD84): unmapped program memory write to EAFC04 = 000E & FFFF [:maincpu] ':maincpu' (02CD94): unmapped program memory write to EAFC04 = 0002 & FFFF [:maincpu] ':maincpu' (02CDA4): unmapped program memory write to EAFC04 = 000C & FFFF [:maincpu] ':maincpu' (02CDB2): unmapped program memory write to EAFC04 = 0821 & FFFF [:maincpu] ':maincpu' (02CDB8): unmapped program memory write to EAFC04 = 000D & FFFF [:maincpu] ':maincpu' (02CDC6): unmapped program memory write to EAFC04 = 2108 & FFFF [:maincpu] ':maincpu' (02CDDE): unmapped program memory write to EAFC04 = 0004 & FFFF [:maincpu] ':maincpu' (02CDEC): unmapped program memory write to EAFC04 = 004C & FFFF [:maincpu] ':maincpu' (02CE2C): unmapped program memory write to EAFC04 = 0005 & FFFF [:maincpu] ':maincpu' (02CE3A): unmapped program memory write to EAFC04 = 008A & FFFF [:maincpu] ':maincpu' (02CE4C): unmapped program memory write to EAFC04 = 0003 & FFFF [:maincpu] ':maincpu' (02CE5A): unmapped program memory write to EAFC04 = 0000 & FFFF [:maincpu] ':maincpu' (02CE72): unmapped program memory write to EAFC04 = 0003 & FFFF [:maincpu] ':maincpu' (02CE80): unmapped program memory write to EAFC04 = 0001 & FFFF [:maincpu] ':maincpu' (02CE90): unmapped program memory write to EAFC04 = 000E & FFFF [:maincpu] ':maincpu' (02CEA0): unmapped program memory write to EAFC04 = 0003 & FFFF [:maincpu] ':maincpu' (02CD84): unmapped program memory write to EAFC00 = 000E & FFFF [:maincpu] ':maincpu' (02CD94): unmapped program memory write to EAFC00 = 0002 & FFFF [:maincpu] ':maincpu' (02CDA4): unmapped program memory write to EAFC00 = 000C & FFFF [:maincpu] ':maincpu' (02CDB2): unmapped program memory write to EAFC00 = 0821 & FFFF [:maincpu] ':maincpu' (02CDB8): unmapped program memory write to EAFC00 = 000D & FFFF [:maincpu] ':maincpu' (02CDC6): unmapped program memory write to EAFC00 = 2108 & FFFF [:maincpu] ':maincpu' (02CDDE): unmapped program memory write to EAFC00 = 0004 & FFFF [:maincpu] ':maincpu' (02CDEC): unmapped program memory write to EAFC00 = 004C & FFFF [:maincpu] ':maincpu' (02CE2C): unmapped program memory write to EAFC00 = 0005 & FFFF [:maincpu] ':maincpu' (02CE3A): unmapped program memory write to EAFC00 = 000A & FFFF [:maincpu] ':maincpu' (02CE4C): unmapped program memory write to EAFC00 = 0003 & FFFF [:maincpu] ':maincpu' (02CE5A): unmapped program memory write to EAFC00 = 0000 & FFFF [:maincpu] ':maincpu' (02CE72): unmapped program memory write to EAFC00 = 0003 & FFFF [:maincpu] ':maincpu' (02CE80): unmapped program memory write to EAFC00 = 0001 & FFFF [:maincpu] ':maincpu' (02CE90): unmapped program memory write to EAFC00 = 000E & FFFF [:maincpu] ':maincpu' (02CEA0): unmapped program memory write to EAFC00 = 0003 & FFFF [:maincpu] ':maincpu' (02D486): unmapped program memory read from EAFC14 & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC14 = 0009 & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC14 = 00C0 & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC14 = 0009 & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC14 = 0080 & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC14 = 0004 & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC14 = 0045 & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC14 = 0001 & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC14 = 0000 & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC14 = 0002 & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC14 = 00C0 & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC14 = 0003 & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC14 = 00C0 & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC14 = 0005 & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC14 = 00E2 & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC14 = 0009 & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC14 = 0001 & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC14 = 000B & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC14 = 0056 & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC14 = 000C & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC14 = 000E & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC14 = 000D & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC14 = 0000 & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC14 = 000E & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC14 = 0002 & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC14 = 0003 & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC14 = 00C1 & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC14 = 0005 & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC14 = 00EA & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC14 = 0000 & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC14 = 0080 & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC14 = 000E & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC14 = 0003 & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC14 = 000F & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC14 = 0000 & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC14 = 0000 & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC14 = 0010 & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC14 = 0000 & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC14 = 0010 & FFFF [:maincpu] ':maincpu' (02D4D0): unmapped program memory write to EAFC14 = 0001 & FFFF [:maincpu] ':maincpu' (02D4DE): unmapped program memory write to EAFC14 = 0010 & FFFF [:maincpu] ':maincpu' (02D4F4): unmapped program memory write to EAFC10 = 0009 & FFFF [:maincpu] ':maincpu' (02D502): unmapped program memory write to EAFC10 = 0040 & FFFF [:maincpu] ':maincpu' (02D4F4): unmapped program memory write to EAFC10 = 0004 & FFFF [:maincpu] ':maincpu' (02D502): unmapped program memory write to EAFC10 = 0045 & FFFF [:maincpu] ':maincpu' (02D4F4): unmapped program memory write to EAFC10 = 0001 & FFFF [:maincpu] ':maincpu' (02D502): unmapped program memory write to EAFC10 = 0000 & FFFF [:maincpu] ':maincpu' (02D4F4): unmapped program memory write to EAFC10 = 0003 & FFFF [:maincpu] ':maincpu' (02D502): unmapped program memory write to EAFC10 = 00C0 & FFFF [:maincpu] ':maincpu' (02D4F4): unmapped program memory write to EAFC10 = 0005 & FFFF [:maincpu] ':maincpu' (02D502): unmapped program memory write to EAFC10 = 0060 & FFFF [:maincpu] ':maincpu' (02D4F4): unmapped program memory write to EAFC10 = 000B & FFFF [:maincpu] ':maincpu' (02D502): unmapped program memory write to EAFC10 = 0056 & FFFF [:maincpu] ':maincpu' (02D4F4): unmapped program memory write to EAFC10 = 000C & FFFF [:maincpu] ':maincpu' (02D502): unmapped program memory write to EAFC10 = 000E & FFFF [:maincpu] ':maincpu' (02D4F4): unmapped program memory write to EAFC10 = 000D & FFFF [:maincpu] ':maincpu' (02D502): unmapped program memory write to EAFC10 = 0000 & FFFF [:maincpu] ':maincpu' (02D4F4): unmapped program memory write to EAFC10 = 000E & FFFF [:maincpu] ':maincpu' (02D502): unmapped program memory write to EAFC10 = 0002 & FFFF [:maincpu] ':maincpu' (02D4F4): unmapped program memory write to EAFC10 = 0003 & FFFF [:maincpu] ':maincpu' (02D502): unmapped program memory write to EAFC10 = 00C1 & FFFF [:maincpu] ':maincpu' (02D4F4): unmapped program memory write to EAFC10 = 0005 & FFFF [:maincpu] ':maincpu' (02D502): unmapped program memory write to EAFC10 = 00EA & FFFF [:maincpu] ':maincpu' (02D4F4): unmapped program memory write to EAFC10 = 0000 & FFFF [:maincpu] ':maincpu' (02D502): unmapped program memory write to EAFC10 = 0080 & FFFF [:maincpu] ':maincpu' (02D4F4): unmapped program memory write to EAFC10 = 000E & FFFF [:maincpu] ':maincpu' (02D502): unmapped program memory write to EAFC10 = 0003 & FFFF [:maincpu] ':maincpu' (02D4F4): unmapped program memory write to EAFC10 = 000F & FFFF [:maincpu] ':maincpu' (02D502): unmapped program memory write to EAFC10 = 0000 & FFFF [:maincpu] ':maincpu' (02D4F4): unmapped program memory write to EAFC10 = 0000 & FFFF [:maincpu] ':maincpu' (02D502): unmapped program memory write to EAFC10 = 0010 & FFFF [:maincpu] ':maincpu' (02D4F4): unmapped program memory write to EAFC10 = 0000 & FFFF [:maincpu] ':maincpu' (02D502): unmapped program memory write to EAFC10 = 0010 & FFFF [:maincpu] ':maincpu' (02D4F4): unmapped program memory write to EAFC10 = 0001 & FFFF [:maincpu] ':maincpu' (02D502): unmapped program memory write to EAFC10 = 0010 & FFFF [:maincpu] ':maincpu' (02D4F4): unmapped program memory write to EAFC10 = 0009 & FFFF [:maincpu] ':maincpu' (02D502): unmapped program memory write to EAFC10 = 0009 & FFFF [:maincpu] ':maincpu' (02D50E): unmapped program memory write to EAFC18 = 0001 & FFFF [:maincpu] ':maincpu' (02CD84): unmapped program memory write to EAFC14 = 000E & FFFF [:maincpu] ':maincpu' (02CD94): unmapped program memory write to EAFC14 = 0002 & FFFF [:maincpu] ':maincpu' (02CDA4): unmapped program memory write to EAFC14 = 000C & FFFF [:maincpu] ':maincpu' (02CDB2): unmapped program memory write to EAFC14 = 0821 & FFFF [:maincpu] ':maincpu' (02CDB8): unmapped program memory write to EAFC14 = 000D & FFFF [:maincpu] ':maincpu' (02CDC6): unmapped program memory write to EAFC14 = 2108 & FFFF [:maincpu] ':maincpu' (02CDDE): unmapped program memory write to EAFC14 = 0004 & FFFF [:maincpu] ':maincpu' (02CDEC): unmapped program memory write to EAFC14 = 004C & FFFF [:maincpu] ':maincpu' (02CE2C): unmapped program memory write to EAFC14 = 0005 & FFFF [:maincpu] ':maincpu' (02CE3A): unmapped program memory write to EAFC14 = 008A & FFFF [:maincpu] ':maincpu' (02CE4C): unmapped program memory write to EAFC14 = 0003 & FFFF [:maincpu] ':maincpu' (02CE5A): unmapped program memory write to EAFC14 = 0000 & FFFF [:maincpu] ':maincpu' (02CE72): unmapped program memory write to EAFC14 = 0003 & FFFF [:maincpu] ':maincpu' (02CE80): unmapped program memory write to EAFC14 = 0001 & FFFF [:maincpu] ':maincpu' (02CE90): unmapped program memory write to EAFC14 = 000E & FFFF [:maincpu] ':maincpu' (02CEA0): unmapped program memory write to EAFC14 = 0003 & FFFF [:maincpu] ':maincpu' (02CD84): unmapped program memory write to EAFC10 = 000E & FFFF [:maincpu] ':maincpu' (02CD94): unmapped program memory write to EAFC10 = 0002 & FFFF [:maincpu] ':maincpu' (02CDA4): unmapped program memory write to EAFC10 = 000C & FFFF [:maincpu] ':maincpu' (02CDB2): unmapped program memory write to EAFC10 = 0821 & FFFF [:maincpu] ':maincpu' (02CDB8): unmapped program memory write to EAFC10 = 000D & FFFF [:maincpu] ':maincpu' (02CDC6): unmapped program memory write to EAFC10 = 2108 & FFFF [:maincpu] ':maincpu' (02CDDE): unmapped program memory write to EAFC10 = 0004 & FFFF [:maincpu] ':maincpu' (02CDEC): unmapped program memory write to EAFC10 = 004C & FFFF [:maincpu] ':maincpu' (02CE2C): unmapped program memory write to EAFC10 = 0005 & FFFF [:maincpu] ':maincpu' (02CE3A): unmapped program memory write to EAFC10 = 000A & FFFF [:maincpu] ':maincpu' (02CE4C): unmapped program memory write to EAFC10 = 0003 & FFFF [:maincpu] ':maincpu' (02CE5A): unmapped program memory write to EAFC10 = 0000 & FFFF [:maincpu] ':maincpu' (02CE72): unmapped program memory write to EAFC10 = 0003 & FFFF [:maincpu] ':maincpu' (02CE80): unmapped program memory write to EAFC10 = 0001 & FFFF [:maincpu] ':maincpu' (02CE90): unmapped program memory write to EAFC10 = 000E & FFFF [:maincpu] ':maincpu' (02CEA0): unmapped program memory write to EAFC10 = 0003 & FFFF [:keyboard:x68k] KB: LED status set to 7f [:keyboard:x68k] KB: LED status set to 7f [:keyboard:x68k] KB: LED status set to 7f [:keyboard:x68k] KB: LED status set to 7f [:keyboard:x68k] KB: LED status set to 7f [:keyboard:x68k] KB: LED status set to 7f | |||||
Relationships
There are no relationship linked to this issue. |
Notes
7
No.21726
Fujix Administrator
Sep 4, 2023, 08:39
|
Corrected some entries. |
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No.21730
Robbbert Moderator
Sep 6, 2023, 15:01
edited on: Sep 6, 2023, 15:14 |
Unable to confirm, because "Steps to Reproduce" info is missing. |
No.21732
Wayder Tester
Sep 8, 2023, 13:08
edited on: Sep 8, 2023, 13:12 |
ex: x68ksupr (Same for X68000 (via cz6bs1), x68kxvi and x68030) [0253_nofd.png] Set (Load) hard1 (SCSI HDD Image) and reset Version 0.253 or earlier Displays Message prompting insertion of floppy disk. Version 0.254 or later Nothing displayed. [0253_infd.png] Set (Load) hard1 (SCSI HDD (.hds) Image), frop1 (.xdf Image) and reset Version 0.253 or earlier floppy and hard disk are loaded. Version 0.254 or later Not working. |
No.21733
ICEknight Tester
Sep 8, 2023, 21:25
edited on: Sep 8, 2023, 21:27 |
Can confirm that something's wrong with the File Manager in this driver. For example: -Load x68000 strider -Once inside the emulation, go to the File Manager and load a floppy to `floppydisk2`. -The disk which was loaded to `floppydisk1` will be gone now. |
No.21735
Robbbert Moderator
Sep 9, 2023, 01:39
|
I still can't confirm, because I don't have any .hds files. x68ksupr and x68kxvi are marked as not working. Tried a few games and disk swaps with the x68000, no notable problems found. With strider specifically, it unloads the system disk by itself at start then complains about it. I was not able to get it to load again as the file manager seems to be not working as I'd expect at this point. I'll set this report as acknowledged. |
No.21746
crazyc Developer
Sep 9, 2023, 22:56
|
It ejects the system disk as a prompt to insert disk b/3 into that drive. |
No.21902
grantek Tester
Jan 5, 2024, 11:27
|
I looked at this a bit from the CZ-6BS1 ("external" SCSI, which conflicts with the "internal" SCSI on models that have it), it started on the switchover from a scsihle implementation of the MB89352 to an NSCSI implementation in mb87030.cpp: https://github.com/mamedev/mame/commit/291e91b8548a48885fb39a6863db5818d5aacf72 I reverted back to the scsihle implementation at HEAD and it works, but I don't know how willing the devs are to restoring a deleted file: https://github.com/grantek/mame/tree/revert-mb89352-log (I reverted the implementation in the internal-SCSI models as well because the implementations use the same device name, but they could technically be split out). From what I can see it's the external SCSI ROM (0xEA0020-0xEA1FFF) hanging on initialisation of the drive before the boot process starts. The NSCSI implementation seems to basically work, I enabled verbose logging on both and got stumped when I saw the X68K is doing a different sequence of SCSI commands on the different SCSI controllers: Old working mb89352.cpp before the switch, as well as with the old file restored into HEAD (reverted-mb89352-error.log): - TEST UNIT READY - TEST UNIT READY again - INQUIRY, requesting 0x20 bytes (up to "ST225N" in t10sbc.cpp) - READ CAPACITY, returning last sector 0x0018494F and 512 bytes/sector - READ LBA 0x00, 1 block - READ LBA 0x04, 1 block - READ LBA 0x40, 1 block NSCSI implementation in mb87030.cpp, with the REQUEST SENSE command hooked up in nscsi/hd.cpp (req_sense-error.log): - TEST UNIT READY once only - REQUEST SENSE, requesting 3 bytes of sense data (this isn't hooked up in MAME head but hooking it up doesn't change anything) - INQUIRY, requesting 0x24 bytes (including the 4-byte version field "1.00") - READ CAPACITY, returning the same last sector 0x0018494F and 512 bytes/sector - READ LBA 0x04, 2 blocks - SCSI Transfer Counter is set to 1024 but stops when it gets down to 728 (296 bytes) Some things I've tried while troubleshooting this: - Hooking up the DMA read and write callbacks - _Outside X68000_ says the CZ-6BS1 uses DMA channel 1, but the old implementation worked without DMA at all. - Hooking up the DMA request line - the schematic on _Outside X68000_ shows this doesn't even connect to the expansion slot, it's only routed through some logic on the board to enable the data path. - Hooking up the REQUEST SENSE command in the NSCSI hd.cpp. None of these really had an effect even though the REQUEST SENSE actually returned some data, but my patches for it are at: https://github.com/grantek/mame/tree/cz6bs1 Some other things I tried: - Changing the "version" byte in the INQUIRY response to match t10sbc.cpp. - Changing the first byte in the INQUIRY response to something other than a SBC direct-access drive. - This seems to break out of the ROM initialisation and the floppy starts to boot, but the SCSI driver on the floppy fails with "Format differs". - The INQUIRY command gets run again from the SCSI driver on the floppy, requesting 0x20 bytes this time. - Detecting this and sending the correct INQUIRY the second time, the SCSI driver just hangs on initialisation after the INQUIRY and no further commands are sent. - Removing all low level delays and bumping the SELECT timeout in nscsi_bus.cpp. The command I used to launch MAME across all of these tests was: ./x68000 -inipath . x68000 -window -flop1 ~/MasterDisk_V2.xdf -exp1 cz6bs1 -hard1 ~/X68000.hds -log [-debug] |